72T1875L5BBI Integrated Device Technology (Idt), 72T1875L5BBI Datasheet - Page 12

• Manufacturer Part Number: 72T1875L5BBI
• Description: FIFO Mem Async/Sync Dual Depth/Width Uni-Dir 16K x 18/32K x 9 144-Pin BGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72T1875L5BBI

• Package: 144BGA
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 288 Kb
• Organization: 16Kx18|32Kx9
• Data Bus Width: 9/18 Bit
• Timing Type: Asynchronous|Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 2.5 V
• Operating Temperature: -40 to 85 °C

AC ELECTRICAL CHARACTERISTICS
(Commercial: V
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Industrial temperature range product for the 5ns speed grade is available as a standard device. All other speed grades are available by special order.
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
C
A
CLK
CLKH
CLKL
DS
DH
ENS
ENH
LDS
LDH
WCSS
WCSH
S
SCLK
SCKH
SCKL
SDS
SDH
SENS
SENH
RS
RSS
HRSS
RSR
RSF
REF
PAES
ERCLK
CLKEN
RCSLZ
RCSHZ
SKEW1
SKEW2
WFF
PAFS
Clock Cycle Frequency (Synchronous)
Data Access Time
Clock Cycle Time
Clock High Time
Clock Low Time
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Load Setup Time
Load Hold Time
WCS setup time
WCS hold time
Clock Cycle Frequency (SCLK)
Serial Clock Cycle
Serial Clock High
Serial Clock Low
Serial Data In Setup
Serial Data In Hold
Serial Enable Setup
Serial Enable Hold
Reset Pulse Width
Reset Setup Time
HSTL Reset Setup Time
Reset Recovery Time
Reset to Flag and Output Time
Write Clock to FF or IR
Read Clock to EF or OR
Write Clock to Synchronous Programmable Almost-Full Flag
Read Clock to Synchronous Programmable Almost-Empty Flag
RCLK to Echo RCLK output
RCLK to Echo REN output
RCLK to Active from High-Z
RCLK to High-Z
Skew time between RCLK and WCLK for EF/OR and FF/IR
Skew time between RCLK and WCLK for PAE and PAF
CC
= 2.5V ± 5%, T
(4)
(3)
Parameter
A
= 0°C to +70°C;Industrial: V
(4)
CC
= 2.5V ± 5%, T
IDT72T18105L4-4
IDT72T18115L4-4
IDT72T18125L4-4
(1)
IDT72T1845L4-4
IDT72T1855L4-4
IDT72T1865L4-4
IDT72T1875L4-4
IDT72T1885L4-4
IDT72T1895L4-4
Min.
4.44
100
Commercial
0.6
2.0
2.0
1.2
0.5
1.2
0.5
1.2
0.5
1.2
0.5
3.5
—
—
45
45
15
30
15
10
—
—
—
—
—
—
—
—
—
5
5
5
4
4
12
⎯ SYNCHRONOUS TIMING
Max.
225
3.4
3.4
3.4
3.4
3.4
3.8
3.4
3.4
3.4
—
—
—
—
—
—
—
—
—
—
—
10
—
—
—
—
—
—
—
—
—
—
—
10
—
—
A
= -40°C to +85°C)
2Kx18/4Kx9, 4Kx18/
IDT72T18105L5
IDT72T18115L5
IDT72T18125L5
Com’l & Ind’l
IDT72T1845L5
IDT72T1855L5
IDT72T1865L5
IDT72T1875L5
IDT72T1885L5
IDT72T1895L5
Min.
100
0.6
2.3
2.3
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
—
—
45
45
15
30
15
10
—
—
—
—
—
—
—
—
—
5
5
5
5
4
4
5
Max.
200
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
—
—
—
—
—
—
—
—
—
—
—
10
—
—
—
—
—
—
—
—
—
—
—
12
—
—
4
(2)
IDT72T18105L6-7 IDT72T18105L10
IDT72T18115L6-7 IDT72T18115L10
IDT72T18125L6-7 IDT72T18125L10
IDT72T1845L6-7
IDT72T1855L6-7
IDT72T1865L6-7
IDT72T1875L6-7
IDT72T1885L6-7
IDT72T1895L6-7
Min.
Commercial
100
0.6
6.7
2.8
2.8
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
—
—
45
45
15
30
15
10
—
—
—
—
—
—
—
—
—
5
5
5
4
5
6
COMMERCIAL AND INDUSTRIAL
150
Max.
3.8
3.8
3.8
3.8
3.8
4.3
3.8
3.8
3.8
—
—
—
—
—
—
—
—
—
—
—
10
—
—
—
—
—
—
—
—
—
—
—
15
—
—
TEMPERATURE RANGES
100
0.6
4.5
4.5
3.0
0.5
3.0
0.5
3.0
0.5
3.0
0.5
Min.
FEBRUARY 10, 2009
—
10
—
45
45
15
30
15
10
—
—
—
—
—
—
—
—
—
Commercial
5
5
5
4
7
8
100
Max.
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
—
—
—
—
—
—
—
—
—
—
—
10
—
—
—
—
—
—
—
—
—
—
—
15
—
—
5
MHz
MHz
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns