72T1875L5BBI Integrated Device Technology (Idt), 72T1875L5BBI Datasheet - Page 44

• Manufacturer Part Number: 72T1875L5BBI
• Description: FIFO Mem Async/Sync Dual Depth/Width Uni-Dir 16K x 18/32K x 9 144-Pin BGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72T1875L5BBI

• Package: 144BGA
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 288 Kb
• Organization: 16Kx18|32Kx9
• Data Bus Width: 9/18 Bit
• Timing Type: Asynchronous|Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 2.5 V
• Operating Temperature: -40 to 85 °C

NOTES:
1. x9 to x9 mode: X =12 for the IDT72T1845, X = 13 for the IDT72T1855, X = 14 for the IDT72T1865, X = 15 for the IDT72T1875, X = 16 for the IDT72T1885, X = 17 for the IDT72T1895,
2. All other modes: X=11 for the IDT72T1845, X = 12 for the IDT72T1855, X = 13 for the IDT72T1865, X = 14 for the IDT72T1875, X = 15 for the IDT72T1885 and X = 16 for the IDT72T1895,
NOTES:
1. This timing diagram is based on programming with a x18 bus width.
2. Overwrites previous offset value.
NOTES:
1. OE = LOW.
2. The timing diagram illustrates reading of offset registers with an output bus width of 18 bits.
3. The offset registers cannot be read on consecutive RCLK cycles. The read must be disabled (REN = HIGH) for a minimum of one RCLK cycle in between register accesses.
SCLK
Q
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
D
RCLK
0
0
SEN
X = 18 for the IDT72T18105, X = 19 for the IDT72T18115 and X = 20 for the IDT72T18125.
X = 17 for the IDT72T18105, X = 18 for the IDT72T18115 and X = 19 for the IDT72T18125.
WCLK
REN
- Q
- D
LD
WEN
LD
SI
17
LD
17
DATA IN OUTPUT REGISTER
t
SCKH
t
CLKH
t
Figure 21. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
SCLK
Figure 20. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
Figure 22. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
CLK
t
t
SCKL
SENS
t
t
LDS
SDS
t
CLKH
BIT 1
t
CLKL
t
LDS
t
ENS
t
CLK
PAE OFFSET
t
t
LDS
t
SENH
A
t
t
ENS
t
LDS
t
CLKL
DS
t
LDH
t
ENH
EMPTY OFFSET
t
t
ENH
t
PAE OFFSET VALUE
LDH
DH
PAF OFFSET
BIT X
(1)
t
DS
44
t
LDS
t
ENS
BIT 1
2Kx18/4Kx9, 4Kx18/
t
A
t
DH
t
LDH
t
ENH
PAE
(2)
OFFSET
t
DS
FULL OFFSET
PAF OFFSET VALUE
COMMERCIAL AND INDUSTRIAL
t
DH
PAF
TEMPERATURE RANGES
BIT X
(2)
t
LDS
OFFSET
FEBRUARY 10, 2009
t
ENS
t
(1)
t
t
ENH
t
SDH
DS
LDH
t
A
t
LDH
t
ENH
PAE OFFSET
5909 drw26
5909 drw24
5909 drw25
t
t
t
ENH
DH
LDH