72T1875L5BBI Integrated Device Technology (Idt), 72T1875L5BBI Datasheet - Page 19

• Manufacturer Part Number: 72T1875L5BBI
• Description: FIFO Mem Async/Sync Dual Depth/Width Uni-Dir 16K x 18/32K x 9 144-Pin BGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72T1875L5BBI

• Package: 144BGA
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 288 Kb
• Organization: 16Kx18|32Kx9
• Data Bus Width: 9/18 Bit
• Timing Type: Asynchronous|Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 2.5 V
• Operating Temperature: -40 to 85 °C

NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
LD
0
0
0
X
1
1
1
WEN
1
1
0
X
1
0
1
REN
1
0
1
1
X
0
1
SEN
0
1
1
1
X
X
X
WCLK
X
X
X
X
RCLK
Figure 3. Programmable Flag Offset Programming Sequence
X
X
X
X
X
Empty Offset
Full Offset
Empty Offset
Full Offset
x18 input
x18 input
Serial shift into registers:
24 bits for the IDT72T1845
26 bits for the IDT72T1855
28 bits for the IDT72T1865
30 bits for the IDT72T1875
32 bits for the IDT72T1885
34 bits for the IDT72T1895
36 bits for the IDT72T18105
38 bits for the IDT72T18115
40 bits for the IDT72T18125
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
(72T18105/115/125)
(72T18105/115/125)
x9 to x9 Mode
x18 input
x18 input
19
I
IDT72T1865,
IDT72T1885,
IDT72T18105,
IDT72T18125
DT72T1845,
Parallel read from registers:
Parallel write to registers:
2Kx18/4Kx9, 4Kx18/
Read Memory
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
No Operation
Write Memory
No Operation
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
x9 input
x9 input
IDT72T1855
IDT72T1875
IDT72T1895
IDT72T18115
Serial shift into registers:
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
22 bits for the IDT72T1845
24 bits for the IDT72T1855
26 bits for the IDT72T1865
28 bits for the IDT72T1875
30 bits for the IDT72T1885
32 bits for the IDT72T1895
34 bits for the IDT72T18105
36 bits for the IDT72T18115
38 bits for the IDT72T18125
All Other Modes
COMMERCIAL AND INDUSTRIAL
Empty Offset (LSB)
Empty Offset
Empty Offset (MSB)
Full Offset (LSB)
Full Offset
Full Offset (MSB)
Empty Offset (LSB)
Empty Offset
Empty Offset (MSB)
Full Offset (LSB)
Full Offset
Full Offset (MSB)
(72T1895/105/115/125)
(72T1895/105/115/125)
TEMPERATURE RANGES
x9 input
x9 input
FEBRUARY 10, 2009
5909 drw06