72T1875L5BBI Integrated Device Technology (Idt), 72T1875L5BBI Datasheet - Page 7

• Manufacturer Part Number: 72T1875L5BBI
• Description: FIFO Mem Async/Sync Dual Depth/Width Uni-Dir 16K x 18/32K x 9 144-Pin BGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72T1875L5BBI

• Package: 144BGA
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 288 Kb
• Organization: 16Kx18|32Kx9
• Data Bus Width: 9/18 Bit
• Timing Type: Asynchronous|Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 2.5 V
• Operating Temperature: -40 to 85 °C

PIN DESCRIPTION
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
Symbol
ASYR
ASYW
BE
D
EF/OR
ERCLK RCLK Echo
EREN
FF/IR
FSEL0
FSEL1
FWFT/
HF
IP
IW
LD
MARK
MRS
OE
OW
PAE
PAF
PFM
SI
0
(1)
–D
(1)
(1)
(1)
(1)
17
(1)
(1)
(1)
(1)
Asynchronous
Read Port
Asynchronous
Write Port
Big-Endian/
Little-Endian
Data Inputs
Empty Flag/
Output Ready
Read Enable Echo HSTL-LVTTL Read Enable Echo output, only available when the Read is setup for Synchronous mode.
Full Flag/
Input Ready
Flag Select Bit 0
Flag Select Bit 1
First Word Fall
Through/Serial In
Half-Full Flag
Interspersed Parity
Input Width
Load
Mark for Retransmit HSTL-LVTTL When this pin is asserted the current location of the read pointer will be marked. Any subsequent Retransmit
Master Reset
Output Enable
Output Width
Programmable
Almost-Empty Flag
Programmable
Almost-Full Flag
Programmable
Flag Mode
Name
HSTL-LVTTL Data inputs for an 18- or 9-bit bus. When in 18- or 9-bit mode, the unused input pins should be tied to GND.
HSTL-LVTTL In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory is empty.
HSTL-LVTTL Read clock Echo output, only available when the Read is setup for Synchronous mode.
HSTL-LVTTL In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is
HSTL-LVTTL During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset, this pin
HSTL-LVTTL HF indicates whether the FIFO memory is more or less than half-full.
HSTL-LVTTL This is a dual purpose pin. During Master Reset, the state of the LD input along with FSEL0 and FSEL1,
HSTL-LVTTL MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Master
HSTL-LVTTL OE provides Asynchronous three-state control of the data outputs, Q
HSTL-LVTTL PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the Empty
HSTL-LVTTL PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored in
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
I/O TYPE
LVTTL
INPUT
LVTTL
INPUT
LVTTL
INPUT
INPUT
LVTTL
INPUT
LVTTL
INPUT
INPUT
LVTTL
INPUT
LVTTL
INPUT
INPUT
INPUT
INPUT
INPUT
LVTTL
INPUT
INPUT
LVTTL
will select Asynchronous operation. If Asynchronous is selected the FIFO must operate in IDT Standard mode.
will select Asynchronous operation.
During Master Reset, a LOW on BE will select Big-Endian operation. A HIGH on BE during Master Reset
In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at the
outputs.
full. In the FWFT mode, the IR function is selected. IR indicates whether or not there is space available for
writing to the FIFO memory.
During Master Reset, this input along with FSEL1 and the LD pin, will select the default offset values for the
programmable flags PAE and PAF. There are up to eight possible settings available.
During Master Reset, this input along with FSEL0 and the LD pin will select the default offset values for the
programmable flags PAE and PAF. There are up to eight possible settings available.
functions as a serial input for loading offset registers. If Asynchronous operation of the read port has been
selected then the FIFO must be setup in IDT Standard mode.
Parity mode.
This pin, along with OW, selects the bus width of the write port. See Table 1 for bus size configuration.
determines one of eight default offset values for the PAE and PAF flags, along with the method by which these
offset registers can be programmed, parallel or serial (see Table 2). After Master Reset, this pin enables writing
to and reading from the offset registers. THIS PIN MUST BE HIGH AFTER MASTER RESET TO WRITE
OR READ DATA TO/FROM THE FIFO MEMORY.
operation will reset the read pointer to this position.
Reset, the FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations,
Synchronous/Asynchronous operation of the read or write port, one of eight programmable flag default settings,
serial or parallel programming of the offset settings, Big-Endian/Little-Endian format, zero latency timing mode,
interspersed parity, and synchronous versus asynchronous programmable flag timing modes.
OE input is the only input that provide High-Impedance control of the data outputs.
This pin, along with IW, selects the bus width of the read port. See Table 1 for bus size configuration.
Offset register. PAE goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n.
the Full Offset register. PAF goes LOW if the number of free locations in the FIFO memory is less than or equal
to m.
During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on
PFM will select Synchronous Programmable flag timing mode.
A HIGH on this input during Master Reset will select Synchronous read operation for the output port. A LOW
A HIGH on this input during Master Reset will select Synchronous write operation for the input port. A LOW
During Master Reset, a LOW on IP will select Non-Interspersed Parity mode. A HIGH will select Interspersed
will select Little-Endian format.
7
Description
2Kx18/4Kx9, 4Kx18/
COMMERCIAL AND INDUSTRIAL
n.
During a Master or Partial Reset the
TEMPERATURE RANGES
FEBRUARY 10, 2009