N25Q128A13BF840E NUMONYX, N25Q128A13BF840E Datasheet - Page 108

• Manufacturer Part Number: N25Q128A13BF840E
• Description: 128MBQUAD IO,XIP VDFPN 8X6 3VT&R
• Manufacturer: NUMONYX

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S
C
DQ0
DQ1
As soon as Chip Select (S) is driven High, the self-timed write NV configuration register
cycle (whose duration is tnvcr) is initiated.
While the Write Non Volatile Configuration register cycle is in progress, it is possible to
monitor the end of the process by polling status Register write in progress (WIP) bit or the
Flag Status Register Program/Erase Controller bit. The write in progress (WIP) bit is 1
during the self-timed Write Non Volatile Configuration register cycle, and is 0 when it is
completed. When the cycle is completed, the write enable latch (WEL) is reset.
The Write Non Volatile Configuration register (WRNVCR) instruction allows the user to
change the values of all the Non Volatile Configuration Register bits, described in
Non-Volatile Configuration
The Write Non Volatile Configuration Register impacts the memory behavior only after the
next power on sequence.
Figure 37. Write NV Configuration Register instruction sequence
Read Volatile Configuration Register
The Read Volatile Configuration Register (RDVCR) instruction allows the Volatile
Configuration Register to be read. See
0
1
High Impedance
2
Instruction
3
4
5
6
Register.
7
7
8
6
9 10 11 12 13 14 15
5
LS Byte
Table 5.: Volatile Configuration
Byte
4
3
2
1
NVCR In
0
15 14 13 12
16 17 18 19 20
MS Byte
Byte
Register.
11 10 9
21 22 23 24
Write_NVCR
Table 3.:
8