N25Q128A13BF840E NUMONYX, N25Q128A13BF840E Datasheet - Page 135

• Manufacturer Part Number: N25Q128A13BF840E
• Description: 128MBQUAD IO,XIP VDFPN 8X6 3VT&R
• Manufacturer: NUMONYX

9.3.4
DQ0
DQ3
DQ1
DQ2
C
S
Figure 72. Read OTP instruction and data-out sequence QIO-SPI
Write Enable (WREN)
The Write Enable (WREN) instruction sets the Write Enable Latch (WEL) bit. Apart form the
parallelizing of the instruction code on the four pins DQ0, DQ1, DQ2 and DQ3, the
instruction functionality is exactly the same as the Write Enable instruction of the Extended
SPI protocol, please refer to
Figure 73. Write Enable instruction sequence QIO-SPI
Instruction
0
1
5
4
6
7
2
DQ0
DQ3
DQ1
DQ2
S
C
1
0
2
3
3
5
4
6
7
4
Section 9.1.9: Write Enable (WREN)
1
0
2
3
5
5
4
6
7
6
Instruction
1
0
2
3
7
0
Quad_Write_Enable
8
1
9 10
Dummy (ex.: 10)
15 16 17 18
5
4
6
7
out 1
Data
1
19
0
3
2
20
4
5
7
for further details.
out n
6
Data
1
21
0
3
2
Quad_Read_OTP
22
4
5
7
6
23
0
1
3
2
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