N25Q128A13BF840E NUMONYX, N25Q128A13BF840E Datasheet - Page 22

• Manufacturer Part Number: N25Q128A13BF840E
• Description: 128MBQUAD IO,XIP VDFPN 8X6 3VT&R
• Manufacturer: NUMONYX

4.3
Note:
Note:
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Quad SPI (QIO-SPI) protocol
Quad SPI (QIO-SPI) protocol: instructions, addresses, and I/O data are always transmitted
on four data lines DQ0, DQ1, W/VPP(DQ2), and HOLD / (DQ3).
The exception is the Program/Erase cycle performed with the VPP, in which case the device
temporarily goes to Extended SPI protocol. Going temporarily into Extended SPI protocol
allows the application either to:
As soon as the VPP pin voltage goes low, the protocol returns to the QIO-SPI protocol.
In QIO-SPI protocol the W and HOLD/ (RESET) functionality is disabled when the device is
selected (S signal low).
When used in the QIO-SPI mode, these devices can be driven by a micro controller in either
of the two following modes:
Please refer to the SPI modes for a detailed description of the 2 modes.
In the Extended SPI protocol only Address and data are allowed to be transmitted on 4 data
lines, However in QIO-SPI protocol, the address, data and instructions are transmitted
across 4 data lines.
This working mode is set in either bit 7 of the Volatile Enhanced Configuration Register
(VECR) or in bit 3 of the Non Volatile Configuration Register (NVCR).
This mode can be set using two ways
check the polling bits: WIP bit in the Status Register or Program/Erase Controller bit in
the Flag Status Register
perform Program/Erase suspend functions.
CPOL=0, CPHA=0
CPOL=1, CPHA=1
Volatile: by setting bit 7 of the VECR to 0, the device enters QIO-SPI protocol
immediately after the Write Enhanced Volatile Configuration Register sequence
completes. The device returns to the default working protocol (defined by the NVCR)
on the next power on.
Default/ Non- Volatile: This is default protocol on power up. By setting bit 3 of the
NVCR to 0, the device enters QIO-SPI protocol on the subsequent power-on. After all
subsequent power-on sequences, the device still starts in QIO-SPI protocol unless bit 3
of the NVCR is set to 1 (default value, corresponding to Extended SPI mode).