N25Q128A13BF840E NUMONYX, N25Q128A13BF840E Datasheet - Page 82

• Manufacturer Part Number: N25Q128A13BF840E
• Description: 128MBQUAD IO,XIP VDFPN 8X6 3VT&R
• Manufacturer: NUMONYX

9.1.4
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DQ0
DQ1
S
C
DQ0
DQ1
S
C
Figure 12. Read Data Bytes at Higher Speed instruction and data-out sequence
Dual Output Fast Read (DOFR)
The Dual Output Fast Read (DOFR) instruction is very similar to the Read Data Bytes at
Higher Speed (FAST_READ) instruction, except that the data are shifted out on two pins
(pin DQ0 and pin DQ1) instead of only one. Outputting the data on two pins instead of one
doubles the data transfer bandwidth compared to the Read Data Bytes at Higher Speed
(FAST_READ) instruction.
The device is first selected by driving Chip Select (S) Low. The instruction code for the Dual
Output Fast Read instruction is followed by a 3-byte address (A23-A0) and a dummy byte,
each bit being latched-in during the rising edge of Serial Clock (C). Then the memory
contents, at that address, are shifted out on DQ0 and DQ1 at a maximum frequency Fc,
during the falling edge of Serial Clock (C).
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out on DQ0 and DQ1. The whole
memory can, therefore, be read with a single Dual Output Fast Read (DOFR) instruction.
When the highest address is reached, the address counter rolls over to 00 0000h, so that
the read sequence can be continued indefinitely.
7
0
32 33 34
6
1
High Impedance
Dummy cycles
5
2
Instruction
3
4
35
4
3
36 37 38 39 40 41 42 43 44 45 46
2
5
1
6
7
0
23
MSB
7
8
22 21
6
9 10
24-bit address
5
DATA OUT 1
4
3
28 29 30 31
3
2
2
1
1
0
0
47
MSB
7
6
5
DATA OUT 2
4
Read_Data_Bytes_Fast_Speed
3
2
1
0
MSB
7