XC3S500E-4PQG208C Xilinx Inc, XC3S500E-4PQG208C Datasheet - Page 100
![FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 208-Pin PQFP](/photos/6/71/67100/pq208_sml.jpg)
XC3S500E-4PQG208C
Manufacturer Part Number
XC3S500E-4PQG208C
Description
FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 208-Pin PQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S500E-4PQG208C
Package
208PQFP
Family Name
Spartan®-3E
Device Logic Cells
10476
Device Logic Units
1164
Device System Gates
500000
Number Of Registers
9312
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
158
Ram Bits
368640
Number Of Logic Elements/cells
10476
Number Of Labs/clbs
1164
Total Ram Bits
368640
Number Of I /o
158
Number Of Gates
500000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-BFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
122-1536 - KIT STARTER SPARTAN-3E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1520
Available stocks
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Price
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Company:
Part Number:
XC3S500E-4PQG208C
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Functional Description
Table 66: Slave Serial Mode Connections
100
HSWAP
M[2:0]
DIN
CCLK
INIT_B
DONE
PROG_B
Pin Name
FPGA Direction
bidirectional I/O
bidirectional I/O
Open-drain
Open-drain
Input
Input
Input
Input
Input
User I/O Pull-Up Control. When
Low during configuration, enables
pull-up resistors in all I/O pins to
respective I/O bank
0: Pull-up during configuration
1: No pull-ups
Mode Select. Selects the FPGA
configuration mode. See
Considerations for the HSWAP,
M[2:0], and VS[2:0]
Data Input.
Configuration Clock. If CCLK
PCB trace is long or has multiple
connections, terminate this output
to maintain signal integrity. See
CCLK Design
Initialization Indicator. Active
Low. Goes Low at start of
configuration during Initialization
memory clearing process.
Released at end of memory
clearing, when mode select pins
are sampled. In daisy-chain
applications, this signal requires
an external 4.7 kΩ pull-up resistor
to VCCO_2.
FPGA Configuration Done. Low
during configuration. Goes High
when FPGA successfully
completes configuration.
Requires external 330 Ω pull-up
resistor to 2.5V.
Program FPGA. Active Low.
When asserted Low for 500 ns or
longer, forces the FPGA to restart
its configuration process by
clearing configuration memory
and resetting the DONE and
INIT_B pins once PROG_B
returns High. Recommend
external 4.7 kΩ pull-up resistor to
2.5V. Internal pull-up value may
be weaker (see
driving externally with a 3.3V
output, use an open-drain or
open-collector driver or use a
current limiting series resistor.
Description
Considerations.
Table
V
Pins.
CCO
78). If
www.xilinx.com
Design
input.
Drive at valid logic level
throughout configuration.
M2 = 1, M1 = 1, M0 = 1 Sampled
when INIT_B goes High.
Serial data provided by host.
FPGA captures data on rising
CCLK edge.
External clock.
Active during configuration. If
CRC error detected during
configuration, FPGA drives
INIT_B Low.
Low indicates that the FPGA is
not yet configured.
Must be High to allow
configuration to start.
During Configuration
DS312-2 (v3.8) August 26, 2009
User I/O
User I/O
User I/O
User I/O
User I/O. If unused in the
application, drive INIT_B
High.
Pulled High via external
pull-up. When High,
indicates that the FPGA
successfully configured.
Drive PROG_B Low and
release to reprogram
FPGA.
After Configuration
Product Specification
R