XC3S500E-4PQG208C Xilinx Inc, XC3S500E-4PQG208C Datasheet - Page 51
![FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 208-Pin PQFP](/photos/6/71/67100/pq208_sml.jpg)
XC3S500E-4PQG208C
Manufacturer Part Number
XC3S500E-4PQG208C
Description
FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 208-Pin PQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S500E-4PQG208C
Package
208PQFP
Family Name
Spartan®-3E
Device Logic Cells
10476
Device Logic Units
1164
Device System Gates
500000
Number Of Registers
9312
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
158
Ram Bits
368640
Number Of Logic Elements/cells
10476
Number Of Labs/clbs
1164
Total Ram Bits
368640
Number Of I /o
158
Number Of Gates
500000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-BFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
122-1536 - KIT STARTER SPARTAN-3E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1520
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S500E-4PQG208C
Manufacturer:
XILINX
Quantity:
362
Company:
Part Number:
XC3S500E-4PQG208C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S500E-4PQG208C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Table 30: Direct Clock Input Connections and Optional External Feedback to Associated DCMs
DS312-2 (v3.8) August 26, 2009
Product Specification
VQ100
CP132
TQ144
PQ208
FT256
FG320
FG400
FG484
VQ100
CP132
TQ144
PQ208
FT256
FG320
FG400
FG484
Package
Package
R
GCLK11
GCLK12
Differential Pair
Differential Pair
Pin Number for Single-Ended Input
P131
P186
XC3S1200E, XC3S1600E: DCM_X1Y3
XC3S1200E, XC3S1600E: DCM_X1Y0
P91
B11
P32
P50
P74
V11
W9
M4
M8
D8
D9
N9
B7
A9
Pin Number for Single-Ended Input
XC3S250E, XC3S500E: DCM_X0Y1
XC3S250E, XC3S500E: DCM_X0Y0
N
P
GCLK10
Bottom Left DCM
GCLK13
P130
P185
W10
A10
C11
Top Left DCM
U11
P90
P33
P51
P75
XC3S100: N/A
XC3S100: N/A
M9
A7
C8
C9
N4
L8
N
P
GCLK14
GCLK9
Differential Pair
Differential Pair
P129
P184
G10
R11
P89
H11
P35
P53
P77
R10
M5
C8
B8
B9
N8
U9
N
P
GCLK15
GCLK8
P128
P183
P88
H10
H12
P36
P54
P78
P10
T11
N5
B8
A8
B8
P8
V9
P
N
Associated Global Buffers
Associated Global Buffers
www.xilinx.com
Clock Line (see
H
D
G
C
B
F
Table
41)
E
A
GCLK7
GCLK0
Differential Pair
Differential Pair
Pin Number for Single-Ended Input
P126
P181
P86
A10
E10
C12
P38
P56
P80
U10
P11
R12
XC3S1200E, XC3S1600E: DCM_X2Y3
XC3S1200E, XC3S1600E: DCM_X2Y0
M6
A9
A9
T9
Pin Number for Single-Ended Input
N
XC3S250E, XC3S500E: DCM_X1Y1
XC3S250E, XC3S500E: DCM_X1Y0
P
XC3S100: DCM_X0Y1
XC3S100: DCM_X0Y0
Bottom Right DCM
GCLK6
GCLK1
Top Right DCM
P125
P180
A10
B10
E11
P85
B12
P39
P57
P81
T10
P12
P12
B9
N6
R9
N
P
Functional Description
GCLK5
GCLK2
Differential Pair
Differential Pair
P123
P178
G11
P84
E10
E12
P40
P58
P82
R10
V10
Y12
C9
P6
P9
F9
N
P
GCLK4
GCLK3
P122
P177
W12
P83
A10
D10
P41
P59
P83
P10
V11
F11
F12
N9
E9
P7
P
N
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