XC3S500E-4PQG208C Xilinx Inc, XC3S500E-4PQG208C Datasheet - Page 165
![FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 208-Pin PQFP](/photos/6/71/67100/pq208_sml.jpg)
XC3S500E-4PQG208C
Manufacturer Part Number
XC3S500E-4PQG208C
Description
FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 208-Pin PQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S500E-4PQG208C
Package
208PQFP
Family Name
Spartan®-3E
Device Logic Cells
10476
Device Logic Units
1164
Device System Gates
500000
Number Of Registers
9312
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
158
Ram Bits
368640
Number Of Logic Elements/cells
10476
Number Of Labs/clbs
1164
Total Ram Bits
368640
Number Of I /o
158
Number Of Gates
500000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-BFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
122-1536 - KIT STARTER SPARTAN-3E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1520
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S500E-4PQG208C
Manufacturer:
XILINX
Quantity:
362
Company:
Part Number:
XC3S500E-4PQG208C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S500E-4PQG208C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Package Overview
Table 125
tion package styles for the Spartan-3E family. Each pack-
age style is available as a standard and an environmentally
friendly lead-free (Pb-free) option. The Pb-free packages
include an extra ‘G’ in the package style name. For exam-
ple, the standard “VQ100” package becomes “VQG100”
when ordered as the Pb-free option. The mechanical
dimensions of the standard and Pb-free packages are simi-
Table 125: Spartan-3E Family Package Options
Selecting the Right Package Option
Spartan-3E FPGAs are available in both quad-flat pack
(QFP) and ball grid array (BGA) packaging options. While
QFP packaging offers the lowest absolute cost, the BGA
Table 126: QFP and BGA Comparison
DS312-4 (v3.8) August 26, 2009
Product Specification
Notes:
1.
Maximum User I/O
Packing Density (Logic/Area)
Signal Integrity
Simultaneous Switching Output (SSO) Support
Thermal Dissipation
Minimum Printed Circuit Board (PCB) Layers
Hand Assembly/Rework
VQ100 / VQG100
PQ208 / PQG208
CP132 / CPG132
TQ144 / TQG144
FG320 / FGG320
FG400 / FGG400
FG484 / FGG484
FT256 / FTG256
Package mass is ±10%.
Package
shows the eight low-cost, space-saving produc-
R
Leads
100
132
144
208
256
320
400
484
Characteristic
Very-thin Quad Flat Pack (VQFP)
Chip-Scale Package (CSP)
Thin Quad Flat Pack (TQFP)
Plastic Quad Flat Pack (PQFP)
Fine-pitch, Thin Ball Grid Array (FBGA)
Fine-pitch Ball Grid Array (FBGA)
Fine-pitch Ball Grid Array (FBGA)
Fine-pitch Ball Grid Array (FBGA)
Type
www.xilinx.com
Quad Flat Pack (QFP)
lar, as shown in the mechanical drawings provided in
Table
Not all Spartan-3E densities are available in all packages.
For a specific package, however, there is a common foot-
print that supports all the devices available in that package.
See the footprint diagrams that follow.
For additional package information, see UG112: Device
Package User Guide.
packages are superior in almost every other aspect, as
summarized in
mends using BGA packaging whenever possible.
Maximum
127.
108
158
190
250
304
376
I/O
66
92
Possible
Good
158
Fair
Fair
Fair
4
Lead
Pitch
(mm)
Table
0.5
0.5
0.5
0.5
1.0
1.0
1.0
1.0
126. Consequently, Xilinx recom-
Area (mm)
30.6 x 30.6
Footprint
8.1 x 8.1
16 x 16
22 x 22
17 x 17
19 x 19
21 x 21
23 x 23
Ball Grid Array (BGA)
Pinout Descriptions
Difficult
Better
Better
Better
Better
Height
(mm)
376
1.60
1.55
1.20
1.10
4.10
2.00
2.43
2.60
4-6
Mass
(g)
0.6
0.1
1.4
0.9
1.4
2.2
2.2
5.3
(1)
165