XC3S500E-4PQG208C Xilinx Inc, XC3S500E-4PQG208C Datasheet - Page 40
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XC3S500E-4PQG208C
Manufacturer Part Number
XC3S500E-4PQG208C
Description
FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 208-Pin PQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S500E-4PQG208C
Package
208PQFP
Family Name
Spartan®-3E
Device Logic Cells
10476
Device Logic Units
1164
Device System Gates
500000
Number Of Registers
9312
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
158
Ram Bits
368640
Number Of Logic Elements/cells
10476
Number Of Labs/clbs
1164
Total Ram Bits
368640
Number Of I /o
158
Number Of Gates
500000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-BFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
122-1536 - KIT STARTER SPARTAN-3E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1520
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S500E-4PQG208C
Manufacturer:
XILINX
Quantity:
362
Company:
Part Number:
XC3S500E-4PQG208C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S500E-4PQG208C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Functional Description
Block RAM Attribute Definitions
A block RAM has a number of attributes that control its
behavior as shown in
Table 24: Block RAM Attributes
Block RAM Data Operations
Writing data to and accessing data from the block RAM are
synchronous operations that take place independently on
each of the two ports.
tions of each port as a result of the block RAM control sig-
nals in their default active-High edges.
Table 25: Block RAM Function Table
40
Initial Content for Data Memory, Loaded
during Configuration
Initial Content for Parity Memory, Loaded
during Configuration
Data Output Latch Initialization
Data Output Latch Synchronous
Set/Reset Value
Data Output Latch Behavior during Write
(see
GSR
1
0
0
0
0
Block RAM Data
EN
X
0
1
1
1
Loaded During Configuration
SSR
Function
X
X
1
1
0
Table
Table 25
Input Signals
WE
Operations)
X
X
0
1
0
24.
CLK
↑
↑
↑
X
X
describes the data opera-
Global Set/Reset Immediately After Configuration
ADDR
Synchronous Set/Reset During Write RAM
addr
addr
X
X
X
(INITP_00 through INITP0F)
Immediately After Configuration
Read RAM, no Write Operation
INITA, INITB (dual-port)
(INIT_00 through INIT3F)
pdata
SRVAL_A, SRVAL_B
DIP
SRVAL (single-port)
Synchronous Set/Reset
INIT (single-port)
X
X
X
X
WRITE_MODE
(dual-port)
Attribute
INITPxx
RAM Disabled
www.xilinx.com
INITxx
Data
DI
X
X
X
X
RAM(pdata)
The waveforms for the write operation are shown in the top
half of
and EN signals enable the active edge of CLK, data at the
DI input bus is written to the block RAM location addressed
by the ADDR lines.
No Chg
SRVAL
SRVAL
DOP
INIT
X
Output Signals
Figure
Each initialization string defines 32 hex values of
the 16384-bit data memory of the block RAM.
Each initialization string defines 32 hex values of
the 2048-bit parity data memory of the block
RAM.
Hex value the width of the chosen port.
Hex value the width of the chosen port.
WRITE_FIRST, READ_FIRST, NO_CHANGE
33,
RAM(data)
No Chg
SRVAL
SRVAL
Figure
INIT
DO
X
34, and
Possible Values
DS312-2 (v3.8) August 26, 2009
RAM(addr)
INITP_xx
← pdata
No Chg
No Chg
No Chg
No Chg
Parity
Figure
RAM Data
Product Specification
35. When the WE
RAM(addr)
INIT_xx
No Chg
No Chg
No Chg
No Chg
← data
Data
R