XC3S500E-4PQG208C Xilinx Inc, XC3S500E-4PQG208C Datasheet - Page 79
![FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 208-Pin PQFP](/photos/6/71/67100/pq208_sml.jpg)
XC3S500E-4PQG208C
Manufacturer Part Number
XC3S500E-4PQG208C
Description
FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 208-Pin PQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S500E-4PQG208C
Package
208PQFP
Family Name
Spartan®-3E
Device Logic Cells
10476
Device Logic Units
1164
Device System Gates
500000
Number Of Registers
9312
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
158
Ram Bits
368640
Number Of Logic Elements/cells
10476
Number Of Labs/clbs
1164
Total Ram Bits
368640
Number Of I /o
158
Number Of Gates
500000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-BFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
122-1536 - KIT STARTER SPARTAN-3E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1520
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S500E-4PQG208C
Manufacturer:
XILINX
Quantity:
362
Company:
Part Number:
XC3S500E-4PQG208C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S500E-4PQG208C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
PROM and the FPGA’s SPI configuration interface. Each
SPI Flash PROM vendor uses slightly different signal nam-
ing. The SPI Flash PROM’s write protect and hold controls
Table 54: Example SPI Flash PROM Connections and Pin Naming
The mode select pins, M[2:0], and the variant select pins,
VS[2:0] are sampled when the FPGA’s INIT_B output goes
High and must be at defined logic levels during this time.
After configuration, when the FPGA’s DONE output goes
High, these pins are all available as full-featured user-I/O
pins.
enable pull-up resistors on all user-I/O pins or High to dis-
DS312-2 (v3.8) August 26, 2009
Product Specification
W
DATA_IN
DATA_OUT
SELECT
CLOCK
WR_PROTECT
HOLD
(see
RESET
(see
RDY/BUSY
(see
P
SPI Flash Pin
Table 54
Similarly, the FPGA’s HSWAP pin must be Low to
Figure
Figure
Figure
W
R
shows the connections between the SPI Flash
53)
54)
54)
MOSI
DIN
CSO_B
CCLK
Not required for FPGA configuration. Must be
High to program SPI Flash. Optional
connection to FPGA user I/O after
configuration.
Not required for FPGA configuration but must
be High during configuration. Optional
connection to FPGA user I/O after
configuration. Not applicable to Atmel
DataFlash.
Only applicable to Atmel DataFlash. Not
required for FPGA configuration but must be
High during configuration. Optional
connection to FPGA user I/O after
configuration. Do not connect to FPGA’s
PROG_B as this will prevent direct
programming of the DataFlash.
Only applicable to Atmel DataFlash and only
available on certain packages. Not required
for FPGA configuration. Output from
DataFlash PROM. Optional connection to
FPGA user I/O after configuration.
FPGA Connection
www.xilinx.com
are not used by the FPGA during configuration. However,
the HOLD pin must be High during the configuration pro-
cess. The PROM’s write protect input must be High in order
to write or program the Flash memory.
able the pull-up resistors. The HSWAP control must remain
at a constant logic level throughout FPGA configuration.
After configuration, when the FPGA’s DONE output goes
High, the HSWAP pin is available as full-featured user-I/O
pin and is powered by the VCCO_0 supply.
In a single-FPGA application, the FPGA’s DOUT pin is not
used but is actively driving during the configuration process.
STMicro
HOLD
N/A
N/A
W
Q
D
S
C
NexFlash
HOLD
CLK
WP
N/A
N/A
DO
CS
DI
Technology
Storage
Silicon
HOLD#
WP#
SCK
CE#
N/A
N/A
SO
Functional Description
SI
RDY/BUSY
DataFlash
RESET
Atmel
SCK
N/A
WP
SO
CS
SI
79