XC5VLX220-1FF1760I Xilinx Inc, XC5VLX220-1FF1760I Datasheet - Page 129

FPGA Virtex®-5 Family 221184 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA

XC5VLX220-1FF1760I

Manufacturer Part Number
XC5VLX220-1FF1760I
Description
FPGA Virtex®-5 Family 221184 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr

Specifications of XC5VLX220-1FF1760I

Package
1760FCBGA
Family Name
Virtex®-5
Device Logic Units
221184
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
800
Ram Bits
7077888
Number Of Logic Elements/cells
221184
Number Of Labs/clbs
17280
Total Ram Bits
7077888
Number Of I /o
800
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1760-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC5VLX220-1FF1760I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Content Initialization - INITP_xx
Output Latches Initialization - INIT (INIT_A or INIT_B)
Table 4-9: Block RAM Initialization Attributes
INITP_xx attributes define the initial contents of the memory cells corresponding to
DIP/DOP buses (parity bits). By default these memory cells are also initialized to all zeros.
The initialization attributes represent the memory contents of the parity bits. The eight
initialization attributes are INITP_00 through INITP_07 for the RAMB18. The 16
initialization attributes are INITP_00 through INITP_0F for the RAMB36. Each INITP_xx is
a 64-digit hex-encoded bit vector with a regular INIT_xx attribute behavior. The same
formula can be used to calculate the bit positions initialized by a particular INITP_xx
attribute.
The INIT (single-port) or INIT_A and INIT_B (dual-port) attributes define the output
latches or output register values after configuration. The width of the INIT (INIT_A and
INIT_B) attribute is the port width, as shown in
encoded bit vectors, and the default value is 0. In cascade mode, both the upper and lower
block RAM should be initialized to the same value.
Attribute
INIT_0E
INIT_00
INIT_01
INIT_02
INIT_0F
INIT_10
INIT_1F
INIT_20
INIT_2F
INIT_30
INIT_3F
INIT_7F
www.xilinx.com
From
12287
12543
16383
32767
3839
4095
4351
8191
8447
255
511
767
Memory Location
Table
4-10. These attributes are hex-
Block RAM Attributes
12032
12288
16128
32512
3584
3840
4096
7936
8192
256
512
To
0
129

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