XC5VLX220-1FF1760I Xilinx Inc, XC5VLX220-1FF1760I Datasheet - Page 295

FPGA Virtex®-5 Family 221184 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA

XC5VLX220-1FF1760I

Manufacturer Part Number
XC5VLX220-1FF1760I
Description
FPGA Virtex®-5 Family 221184 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr

Specifications of XC5VLX220-1FF1760I

Package
1760FCBGA
Family Name
Virtex®-5
Device Logic Units
221184
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
800
Ram Bits
7077888
Number Of Logic Elements/cells
221184
Number Of Labs/clbs
17280
Total Ram Bits
7077888
Number Of I /o
800
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1760-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC5VLX220-1FF1760I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Transmitter Termination
Receiver Termination
The Virtex-5 FPGA LVDS transmitter does not require any external termination.
lists the allowed attributes corresponding to the Virtex-5 FPGA LVDS current-mode
drivers. Virtex-5 FPGA LVDS current-mode drivers are a true current source and produce
the proper (EIA/TIA compliant) LVDS signal.
Figure 6-87
50 Ω transmission lines.
X-Ref Target - Figure 6-87
Figure 6-88
50 Ω transmission lines.
X-Ref Target - Figure 6-88
Table 6-36
Table 6-36: Allowed Attributes of the LVDS I/O Standard
IOSTANDARD
DIFF_TERM
Attributes
LVDS_25
External Termination
lists the available Virtex-5 FPGA LVDS I/O standards and attributes supported.
is an example of a differential termination for an LVDS receiver on a board with
is an example of differential termination for an LVDS receiver on a board with
Figure 6-88: LVDS_25 With DIFF_TERM Receiver Termination
LVDS_25
IOB
Figure 6-87: LVDS_25 Receiver Termination
www.xilinx.com
IOB
IBUFDS/IBUFGDS
0
TRUE, FALSE
Z
Z
0
0
R DIFF = 2Z 0 = 100Ω
= 50Ω
= 50Ω
Specific Guidelines for I/O Supported Standards
0
Z 0
Z 0
LVDS_25, LVDSEXT_25
Primitives
IOB
R DIFF = 100Ω
IOB
OBUFDS/OBUFTDS
+
N/A
LVDS_25
LVDS_25
+
ug190_6_81_030506
ug190_6_82_030506
Data in
Table 6-36
295

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