XC5VLX220-1FF1760I Xilinx Inc, XC5VLX220-1FF1760I Datasheet - Page 150

• Manufacturer Part Number: XC5VLX220-1FF1760I
• Description: FPGA Virtex®-5 Family 221184 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX220-1FF1760I

• Package: 1760FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 221184
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 800
• Ram Bits: 7077888
• Number Of Logic Elements/cells: 221184
• Number Of Labs/clbs: 17280
• Total Ram Bits: 7077888
• Number Of I /o: 800
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1760-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Chapter 4: Block RAM
Table 4-20: FIFO Timing Parameters (Continued)
150
Notes:
1. T
2. In the Virtex-5 FPGA Data Sheet, T
3. In the Virtex-5 FPGA Data Sheet, T
4. T
5. In the Virtex-5 FPGA Data Sheet, WRITE and READ enables are combined into T
T
T
Reset to Out
T
T
T
T
T
T
T
T
RCKO_RDCOUNT
RCKO_WRCOUNT
RCO_AEMPTY
RCO_AFULL
RCO_EMPTY
RCO_FULL
RCO_RDERR
RCO_WRERR
RCO_RDCOUNT
RCO_WRCOUNT
combined into T
RCKO_DO
RCDCK_DI
Parameter
FIFO Timing Characteristics
includes parity output (T
includes parity inputs (T
(3)
RCKO_FLAGS
(3)
Clock to read pointer
output
Clock to write pointer
output
Reset to almost empty
output
Reset to almost full
output
Reset to empty output
Reset to full output
Reset to read error
output
Reset to write error
output
Reset to read pointer
output
Reset to write pointer
output
The various timing parameters in the FIFO are described in this section. There is also
additional data on FIFO functionality. The timing diagrams describe the behavior in these
six cases.
•
•
•
•
•
•
.
Case 1: Writing to an Empty FIFO
Case 2: Writing to a Full or Almost Full FIFO
Case 3: Reading From a Full FIFO
Case 4: Reading From An Empty or Almost Empty FIFO
Case 5: Resetting All Flags
Case 6: Simultaneous Read and Write for Multirate FIFO
Function
RCKO_AEMPTY
RCKO_RDCOUNT
RCKO_DOP
RCDCK_DIP
).
).
, T
and T
RCKO_AFULL
WRCOUNT
WRCOUNT
RDCOUNT
RDCOUNT
AEMPTY
WRERR
Control
EMPTY
RCKO_WRCOUNT
www.xilinx.com
AFULL
RDERR
Signal
FULL
, T
RCKO_EMPTY
Time after RDCLK that the Read pointer signal is
stable at the RDCOUNT outputs of the FIFO.
stable at the WRCOUNT outputs of the FIFO.
Time after reset that the Almost Empty signal is stable
at the ALMOSTEMPTY outputs of the FIFO.
Time after reset that the Almost Full signal is stable at
the ALMOSTFULL outputs of the FIFO.
Time after reset that the Empty signal is stable at the
EMPTY outputs of the FIFO.
Time after reset that the Full signal is stable at the
FULL outputs of the FIFO.
Time after reset that the Read error signal is stable at
the RDERR outputs of the FIFO.
Time after reset that the Write error signal is stable at
the WRERR outputs of the FIFO.
Time after reset that the Read pointer signal is stable
at the RDCOUNT outputs of the FIFO.
Time after reset that the Write pointer signal is stable
at the WRCOUNT outputs of the FIFO.
Time after WRCLK that the Write pointer signal is
are combined into T
, T
RCKO_FULL
RCCK_EN
.
, T
RCKO_POINTERS
RCKO_RDERR
Description
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
, T
RCKO_WRERR
.
are