XC5VLX220-1FF1760I Xilinx Inc, XC5VLX220-1FF1760I Datasheet - Page 30

• Manufacturer Part Number: XC5VLX220-1FF1760I
• Description: FPGA Virtex®-5 Family 221184 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX220-1FF1760I

• Package: 1760FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 221184
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 800
• Ram Bits: 7077888
• Number Of Logic Elements/cells: 221184
• Number Of Labs/clbs: 17280
• Total Ram Bits: 7077888
• Number Of I /o: 800
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1760-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Chapter 1: Clock Resources
X-Ref Target - Figure 1-2
30
IGNORE0
IGNORE1
CE0
CE1
S0
S1
I0
I1
O
The timing diagram in
BUFGCTRL primitives. Exact timing numbers are best found using the speed specification.
•
•
•
•
•
Other capabilities of BUFGCTRL are:
•
•
•
at I0
Before time event 1, output O uses input I0.
At time T
deasserted Low. At about the same time, both CE1 and S1 are asserted High.
At time T
to Low transition of I0 (event 2) followed by a High to Low transition of I1.
At time event 4, IGNORE1 is asserted.
At time event 5, CE0 and S0 are asserted High while CE1 and S1 are deasserted Low.
At T
requiring a High to Low transition of I1.
Pre-selection of the I0 and I1 inputs are made after configuration but before device
operation.
The initial output after configuration can be selected as either High or Low.
Clock selection using CE0 and CE1 only (S0 and S1 tied High) can change the clock
selection without waiting for a High to Low transition on the previously selected
clock.
T
BCCKO_O
1
BCCKO_O
Figure 1-2: BUFGCTRL Timing Diagram
T
BCCCK_CE
BCCCK_CE
BCCKO_O
2
, after time event 6, output O has switched from I1 to I0 without
, after time event 3, output O uses input I1. This occurs after a High
Figure 1-2
, before the rising edge at time event 1, both CE0 and S0 are
T
BCCKO_O
www.xilinx.com
3
Begin I1
illustrates various clock switching conditions using the
4
5
Begin I0
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
T
BCCKO_O
6
ug190_1_02_071707