STLC5466 STMicroelectronics, STLC5466 Datasheet - Page 41

• Manufacturer Part Number: STLC5466
• Description: RF Wireless Misc Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom ICr

Specifications of STLC5466

• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-176
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PS
SCR : Scrambler/ Descrambler
VI.9 - Connection Memory Address Register
This 16 bit register is constituted by two registers: DESTINATION REGISTER (DSTR) and ACCESS
MODE REGISTER (AMR) respectively 8 bits and 6 bits.
DESTINATION REGISTER (DSTR)
Only when DSTR is written by the microprocessor, a memory access is launched.
DSTR has two use modes depending on CM (bit of CMAR).
CM = 1, access to connection memory (read or write);
When CM = 1, OTS 0/4 and OM 0/2 bits are defined hereafter:
OTS 0/4 : Output time slot 0/4 define OTSy with: 0
OM0/2 : Output Time Division Multiplex 0/2 define OTDMq with: 0
See table hereafter when DR04, DR24, DR44 and/or DR64 are at “1”; these bits of SMCR define the TDMs
at 4 Mbit/s.
bit15
Nu
: Programmable Synchronization
Nu
If PS = 1, Programmable Synchronization Signal Pin is at “1” during the bit time defined by OTSy
and OTDMq.
For OTSy and OTDMq with y = q = 0, PSS pin is at “1” during the first bit of the frame defined by
the Frame synchronization Signal (FS).
If PS = 0, PSS Pin is at “0” during the bit time defined by OTSy and OTDMq.
SCR=1, the scrambler or the descrambler are enabled. Both of them are located after the switch-
ing matrix.
The scrambler is enabled when the output timeslot defined by the destination register (DSTR) is
an output timeslot belonging to any TDM except the two GCI multiplexes; the contents of this out-
put timeslot will be scrambled in accordance with the IUT-T V.29 Rec.
The descrambler is enabled when the output timeslot defined by the destination register (DSTR)
is an output timeslot belonging to the two GCI multiplexes except any TDM; the contents of this
output timeslot is descrambled in accordance with the IUT-T V.29 Rec.
Only 32 timeslots of 256 can be scrambled or/and descrambled:
GCI side, only B1 and B2 can be selected in each GCI channel (16 GCI channels are available:
8 per GCI multiplex).
*TDM side, it is forbidden to select a given timeslot more than once when several TDMs are se-
lected.
SCR=0, the scrambler or the descrambler are disabled; the contents of output timeslots are not
modified.
ACCESS MODE REGISTER (AMR)
TC
CACL CAC
BID
CM
After reset (0800)
READ OM2
bit8
y
bit7
31;
H
OM1
DESTINATION REGISTER (DSTR)
OM0 OTS4 OTS3 OTS2 OTS1 OTS0
q
7.
CMAR (10)
STLC5466
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bit0
H