STLC5466 STMicroelectronics, STLC5466 Datasheet - Page 62

• Manufacturer Part Number: STLC5466
• Description: RF Wireless Misc Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom ICr

Specifications of STLC5466

• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-176
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STLC5466
A16/23: These 8 bits define two areas of the shared Memory; each area is multiple of 64Kbytes. The
VI.35 - Time Slot Assigner Address Register 2
This register concerns the second 32 HDLC controller named HDLC2 connected to input6/output6 of the
switching matrix.
READ
TS0/4
HDI
• N.B. After software reset (bit 2 of IDCR Register) or pin reset the automate above mentioned is working.
VI.36 - Time Slot Assigner Data Register 2
This register concerns the second 32 HDLC controller named HDLC2 connected to input6/output6 of the
switching matrix
CH0/4
V1/8
62/130
bit15
bit15
TS4
V11
The automate is stopped when the microprocessor writes TAAR Register with HDI = 0.
TS3
V10
: READ MEMORY
: TIME SLOTS0/4
: HDLC2 INIT
: CHANNEL0/4
: VALIDATION
shared Memory is split in two parts:
the upper part of the shared Memory is affected to the first half part of the Fetch Memory located
in the microprocessor interface,
the lower part is affected to the second half part of the Fetch Memory.
Particular case: A16/23=0. One area of the shared Memory is defined, the two parts of the Fetch
Memory are merged.
READ = 1, Read Time slot Assigner Memory 2.
READ = 0, Write Time slot Assigner Memory 2.
These five bits define one of 32 time slots in which a channel is set-up or not.
HDI = 1, TSA2 Memory, Tx HDLC2, Tx DMA2, Rx HDLC2, Rx DMA2 are reset. An automate
writes data from Time slot Assigner Data Register 2 (TADR2) (except CH0/4 bits) into each
TSA Memory location. If the microprocessor reads Time slot Assigner Memory 2 after HDLC2
INIT, CH0/4 bits of Time slot Assigner Data Register are identical to TS0/4 bits of Time slot
Assigner Address Register 2.
HDI = 0, Normal state.
These five bits define one of 32 channels associated to time slot defined by the previous Reg-
ister 2(TAAR2).
The logical channel CHx is constituted by each subchannel 1 to 8 and validated by V1/8 bit at
1 respectively.
V1 to V8 are at “0’: the subchannels are ignored.
V1 corresponds to the first bit received during the current time slot.
V1 at 1: the first bit of the current time slot is taken into account in reception and in transmission
the first bit transmitted is taken into account.
V8 at 1: the last bit of the current time slot is taken into account in reception the last bit received
and in transmission the last bit transmitted in transmission.
TS2
V9
TS1
V8
TS0 READ
V7
V6
Nu
V5
After reset (0100)
After reset (0000)
HDI
bit8
bit8
V4
bit7
bit7
V3
r
H
H
V2
e
V1
s
CH4
e
CH3
r
CH2
v
TAAR2 (54)
TADR2 (56)
CH1
e
CH0
bit0
bit0
d
H
H