STLC5466 STMicroelectronics, STLC5466 Datasheet - Page 81

• Manufacturer Part Number: STLC5466
• Description: RF Wireless Misc Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom ICr

Specifications of STLC5466

• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-176
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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FIGURES associated with text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
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CLOCK and TDMs TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
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SDRAM MEMORY TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
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MICROPROCESSOR TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
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MHDLC Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Variable delay through the matrix with ITDM=1 . . . . . . . . . . . . . . . . . . . . 84
Variable delay through the matrix with ITDM=0 . . . . . . . . . . . . . . . . . . . . 85
Constant delay through the matrix with SI=1. . . . . . . . . . . . . . . . . . . . . . . 86
Downstream switching at 32 kb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Upstream switching at 32 kb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Upstream and downstream switching at 16 Kbit/s . . . . . . . . . . . . . . . . . . 89
D, C/I and Monitor channel path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
GCI channel to/from ISDN channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
From GCI channels to ISDN channels . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
From ISDN channels to GCI channels . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Multi-HDLC connected to mP with multiplexed buses. . . . . . . . . . . . . . . . 94
Multi-HDLC connected to mP with non multiplexed buses . . . . . . . . . . . . 94
Microprocessor interface for INTEL 80C188 . . . . . . . . . . . . . . . . . . . . . . . 95
Microprocessor interface for INTEL 80C186 . . . . . . . . . . . . . . . . . . . . . . . 95
Microprocessor interface for MOROLA 68000 . . . . . . . . . . . . . . . . . . . . . 96
Microprocessor interface for MOROLA 68020 . . . . . . . . . . . . . . . . . . . . . 96
Microprocessor interface for ST9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Microprocessor interface for INTEL 386EX. . . . . . . . . . . . . . . . . . . . . . . . 97
Ex1; different clocks for Multi-HDLC and mP . . . . . . . . . . . . . . . . . . . . . . 98
Ex2; synchronous clock for Multi-HDLC and mP . . . . . . . . . . . . . . . . . . . 98
4Mx16 SDRAM memory organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
First example, 8Mx16 SDRAM memory organisation . . . . . . . . . . . . . . . 100
Second example, 8Mx16 SDRAM memory organisation . . . . . . . . . . . . 101
Third example, 8Mx16 SDRAM memory organisation . . . . . . . . . . . . . . 102
Chain of n Multi-HDLC components . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
MHDLC clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
VCXO frequency synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
The three circular interrupt memories . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Clocks received and delivered by the Multi-HDLC . . . . . . . . . . . . . . . . . 106
Synchronization signals received by the Multi-HDLC . . . . . . . . . . . . . . . 107
GCI Synchro signal delivered by the Multi-HDLC . . . . . . . . . . . . . . . . . . 108
V* Synchronisation signal delivered by the Multi-HDLC . . . . . . . . . . . . . 109
Signals exchanged between SDRAM controller and SDRAM. . . . . . . . . 110
ST 9 read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
ST 9 write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
ST10 (C16x) read cycle; multiplexed A/D . . . . . . . . . . . . . . . . . . . . . . . . 113
ST10 (C16x) write cycle; multiplexed A/D . . . . . . . . . . . . . . . . . . . . . . . . 114
LIST OF FIGURES
STLC5466
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