STLC5466 STMicroelectronics, STLC5466 Datasheet - Page 55

• Manufacturer Part Number: STLC5466
• Description: RF Wireless Misc Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom ICr

Specifications of STLC5466

• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-176
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

VI.25 - Transmit Monitor Interrupt Register
When the microprocessor read this register, this register is reset (0000)
MIxy : Transmit Monitor Channel x Interrupt, Multiplex y with:
VI.26 - Memory Interface Configuration Register
REF
P1 E0/1
P2 E0/1
P3 E0/1
P4 E0/1
bit15
MI71
bit15
P41
:
MI61
P40
y = 0, GCI CHANNEL belongs to the multiplex TDM4 and y = 1 to TDM5.
MIxy = 1 when:
– a word has been transmitted and pre-acknowledged by the Transmit Monitor Channel xy (In
– the message has been aborted by the remote receive Monitor Channel or
– the Timer has reached one millisecond (in accordance with TIV bit of TMAR) by IM3 bit of IMR.
When MIxy goes to “1”, the Interrupt MTX bit of IR is generated. Interrupt MTX can be masked.
REF=1, SDRAM REFRESH is validated
REF=0, SDRAM REFRESH is not validated
PRIORITY 1 for entity defined by E0/1
PRIORITY 2 for entity defined by E0/1
PRIORITY 3 for entity defined by E0/1
PRIORITY 4 for entity defined by E0/1
MEMORY REFRESH
Entity definition:
PRIORITY 5 is the last priority for SDRAM Refresh if validated. SDRAM Refresh obtains
PRIORITY 0 (the first priority) automatically when the first half cycle is spend without access
to memory.
After reset (E400)H,
the Rx DMA Controller has the PRIORITY 1
the Microprocessor has the PRIORITY 2
the Tx DMA Controller has the PRIORITY 3
the Interrupt Controller has the PRIORITY 4
this case the Transmit Monitor Data Register (TMDR) is available to transmit a new word) or
x
E 1
MI51
P31
0
0
1
1
7, 1 of 8 GCI CHANNELS belonging to the same multiplex TDM4 or TDM5
MI41
P30
TDM5
E 0
0
1
0
1
MI31
P21
Rx DMA Controller
Interrupt Controller
Tx DMA Controller
MI21
P20
Microprocessor
Entity
MI11
P11
After reset (0000)
After reset (0000)
MI01
P10
bit8
bit8
MI70
bit7
bit7
Nu
H
H
MI60
Nu
MI50
Nu
H.
MI40
Nu
TDM4
MI30
Nu
MI20
Nu
STLC5466
MI10
MICR (32)
TMIR (30)
Nu
55/130
MI00
REF
bit0
bit0
H
H