PSB50505EV13GXT Lantiq, PSB50505EV13GXT Datasheet - Page 115
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PSB50505EV13GXT
Manufacturer Part Number
PSB50505EV13GXT
Description
Manufacturer
Lantiq
Datasheet
1.PSB50505EV13GXT.pdf
(290 pages)
Specifications of PSB50505EV13GXT
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5.6
The IWE8 needs to be connected to an external synchronous SRAM of 64k x 33 bits with
parity protection or 64k x 32 bits without parity protection.
For proper operation FT (Flow Through) SSRAM is needed. Pipelined SSRAM can not
be used, as this type has additional registered outputs.
A possible connection with 1 SRAM 64k x 36 component is shown in
.
Figure 34
The IWE8 has a fixed RAM interface cycle of 12 clock periods. A sequence of
6 consecutive read cycles (addresses AR1 to AR6), a dummy address cycle and
5 consecutive write cycles (addresses AW1 to AW5) is continuously repeated. The
timing of RMADC and RMOE is always fixed as shown in
reads data from the external RAM or writes data into the external RAM is controlled by
the RMCS and RMWR signals. In
IWE8, and data W1 and W3 are actually written into the external RAM.
Data Sheet
External RAM Interface
External RAM Connection
IWE8
RMADR[0-15]
RMDAT[0-32]
RMADC
RMCLK
RMWR
RMOE
RMCS
Figure
115
35, data R1 and R3 are actually read by the
PXB 4219E, PXB 4220E, PXB 4221E
CLK
A[0-15]
CS
WR
OE
ADSC
D[0-35]
SRAM 64K x 36
Figure
Interface Description
35. Whether the IWE8
Figure
IWE8, V3.4
34.
2003-01-20
erc
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