LAN9220-ABZJ Standard Microsystems (SMSC), LAN9220-ABZJ Datasheet - Page 129

• Manufacturer Part Number: LAN9220-ABZJ
• Description: 10/100 NON-PCI ETHERNET CONTROLLER
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9220-ABZJ

• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Compliant

16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support
Datasheet
SMSC LAN9220
6.2.2
RX Status FIFO
TX Status FIFO
RX Data FIFO
RX_DP_CTRL
READING...
RX_DROP
REGISTER NAME
AFTER
MAC_CSR_DATA
MAC_CSR_CMD
E2P_DATA
RX_DROP
AFC_CFG
E2P_CMD
Special Restrictions on Back-to-Back Read Cycles
There are also restrictions on specific back-to-back read operations. These restrictions concern
reading specific registers after reading resources that have side effects. In many cases there is a delay
between reading the LAN9220, and the subsequent indication of the expected change in the control
register values.
In order to prevent the host from reading stale data on back-to-back reads, minimum wait periods have
been established. These periods are specified in
processor is required to wait the specified period of time between read operations of specific
combinations of resources. The wait period is dependant upon the combination of registers being read.
Performing "dummy" reads of the BYTE_TEST register is a convenient way to guarantee that the
minimum wait time restriction is met.
required for back-to-back read operations. The number of BYTE_TEST reads in this table is based on
the minimum timing for Tcycle (165ns). For microprocessors with slower busses the number of reads
may be reduced as long as the total time is equal to, or greater than the time specified in the table.
Dummy reads of the BYTE_TEST register are not required as long as the minimum time period is met.
Note 6.1
This restriction is only applicable after a fast-forward operation has been completed and
the RX_FFWD bit has been cleared. Refer to
Forward," on page 63
WAIT FOR THIS MANY
Table 6.1 Read After Write Timing Rules (continued)
NS…
165
165
165
330
330
Table 6.2 Read After Read Timing Rules
FOLLOWING ANY WRITE CYCLE
MINIMUM WAIT TIME FOR READ
for more information.
DATASHEET
(IN NS)
Table 6.2
165
165
165
165
165
0
129
OR PERFORM THIS MANY
READS OF BYTE_TEST…
(ASSUMING Tcycle OF
Table 6.2, "Read After Read Timing
also shows the number of dummy reads that are
165NS)
1
1
1
2
2
Section 3.13.1.1, "Receive Data FIFO Fast
(ASSUMING T
NUMBER OF BYTE_TEST
BEFORE READING...
READS
RX Status FIFO
TX Status FIFO
RX_FIFO_INF
RX_FIFO_INF
TX_FIFO_INF
CYCLE
0
1
1
1
1
1
RX_DROP
Note 6.1
Revision 2.7 (03-15-10)
Rules". The host
OF 165NS)