L80223/D LSI, L80223/D Datasheet - Page 138

• Manufacturer Part Number: L80223/D
• Manufacturer: LSI

Specifications of L80223/D

• Lead Free Status / RoHS Status: Not Compliant

A-16
All the GND pins should also be connected together as closely as
possible to the device with a large ground plane. If the GND pins vary in
potential by even a small amount, noise and latchup can result. The GND
pins should be kept to within 50 mV of each other.
A 0.01–0.1 F decoupling capacitor should be connected between each
V
0.5 inches. The value should be chosen based on whether the noise
from V
be to use two decoupling capacitors on each V
for low-frequency and one 0.001 Ffor high-frequency noise on the power
supply.
The V
Figure A.1
common-mode noise injection from the supply into the twisted-pair cable.
It is recommended that a 0.01 F decoupling capacitor be placed
between the center tap V
capacitor should be physically placed as close as possible to the
transformer center tap, preferably within 0.5 inches
The PCB layout and power supply decoupling discussed above should
provide sufficient decoupling to achieve the following when measured at
the device:
Application Information
DD
The resultant AC noise voltage measured across each V
should be less than 100 mV p-p
All V
All GND pins should be within 50 mV p-p of each other.
/GND set as closely as possible to the device pins, preferably within
DD
DD
DD
-GND is high- or low-frequency. A conservative approach would
connection to the transmit transformer center tap shown in
through
pins should be within 50 mV p-p of each other
Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Figure A.3
DD
and the GND plane. This decoupling
has to be well decoupled to minimize
DD
/GND set, one 0.1 F
DD
/GND set