L80223/D LSI, L80223/D Datasheet - Page 27

• Manufacturer Part Number: L80223/D
• Manufacturer: LSI

Specifications of L80223/D

• Lead Free Status / RoHS Status: Not Compliant

2.3.2 Controller Interface
2.3.2.1 High Impedance Control
2.3.2.2 MII Interface
This section describes the controller interface operation.
When the RX_EN pin is LOW, the following controller interface outputs
are placed in the high impedance state:
The device has an MII interface to an external Ethernet Media Access
Controller (MAC).
MII (100 Mbits/s) – The MII is a nibble-wide packet data interface
defined in IEEE 802.3 and shown in
the MII requirements outlined in IEEE 802.3. The L80227 can directly
connect, without any external logic, to any Ethernet controller or other
device that also complies with the IEEE 802.3 MII specifications.
The MII interface contains the following signals:
Block Diagram Description
RX_CLK
RXD[3:0]
RX_DV
RX_ER
COL
Transmit data bits (TXD[3:0])
Transmit clock (TX_CLK)
Transmit enable (TX_EN)
Transmit error (TX_ER)
Receive data bits (RXD[3:0])
Receive clock (RX_CLK)
Carrier sense (CRS)
Receive data valid (RX_DV)
Receive data error (RX_ER)
Collision (COL).
Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Figure
2.3. The L80227 meets all
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