L80223/D LSI, L80223/D Datasheet - Page 17

• Manufacturer Part Number: L80223/D
• Manufacturer: LSI

Specifications of L80223/D

• Lead Free Status / RoHS Status: Not Compliant

1.2 Features
Using the on-chip AutoNegotiation algorithm, the device can
automatically configure the PHY channel to independently operate in
100 Mbits/s or 10 Mbits/s operation in either full- or half-duplex mode.
The device uses the Management Interface (MI) serial port to access
eight 16-bit registers in the PHY. These registers comply to Clause 22 of
IEEE 802.3u and contain bits and fields that reflect configuration inputs,
status outputs, and device capabilities.
The device is ideally suited as a media interface for
10BASE-T/100BASE-TX repeaters, routers, PCMCIA cards, NIC cards,
networked modems, and other end station applications.
The device is implemented in either 0.35 or 0.30 micron CMOS
technology and operates on a 3.3 V power supply.
The following list summarizes the salient features of the devices:
Features
Single-chip solution for a 10BASE-T/100BASE-TX PHY
Dual speed: 10/100 Mbit/s
Half-duplex or full-duplex operation
MII interface to Ethernet MAC
Management Interface (MI) for configuration and status
AutoNegotiation for 10/100 Mbit/s, full/half duplex operation
AutoNegotiation Advertisement control through pins
All applicable IEEE 802.3, 10BASE-T and 100BASE-TX
specifications are met
On-chip wave shaping (no external filters required)
Adaptive equalizer for 100BASE-TX operation
Baseline wander correction
Minimum number of external components
LEDs are individually programmable to reflect any the following
events:
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