L80223/D LSI, L80223/D Datasheet - Page 25

• Manufacturer Part Number: L80223/D
• Manufacturer: LSI

Specifications of L80223/D

• Lead Free Status / RoHS Status: Not Compliant

Table 2.3
1. First preamble nibble received. Depending on the mode, the device may eliminate either all or some
2. First SFD nibble received.
3. First data nibble received.
4. D0 through D7 are the first 8 bits of the data field.
2.2.2.2 10BASE-T Operation
Signals
RX_DV
RXDO
RXD1
RXD2
RXD3
of the preamble nibbles, up to the first SFD nibble.
X
X
X
X
0
Receive Preamble and SFD Bits at MAC Nibble Interface
1
0
1
0
1
1
1
0
1
0
1
In 100BASE-TX receive operation, the TP receiver takes incoming
encoded and scrambled MLT3 data from the twisted-pair cable, removes
any high-frequency noise from the input, equalizes the input signal to
compensate for the effects of the cable, performs baseline wander
correction, qualifies the data with a squelch algorithm, and converts the
data from MLT3-encoded levels to internal digital levels. The output of the
receiver then goes to a clock and data recovery block that recovers a
clock from the incoming data, uses the clock to latch valid data into the
device, and converts the data back to NRZ format. The 4B5B decoder
and descrambler then decodes and descrambles the NRZ data,
respectively, and sends it out of the Controller Interface to an external
Ethernet controller. The format of the received data at the Controller
interface is as shown in
10BASE-T operation is similar to the 100BASE-TX operation except
Overview
1
0
1
0
1
there is no scrambler/descrambler
the encoder/decoder is Manchester instead of 4B5B
the data rate is 10 Mbits/s instead of 100 Mbits/s,
the twisted-pair symbol data is two-level Manchester instead of
ternary MLT-3.
the transmitter generates link pulses during the idle period
the transmitter detects the jabber condition
the receiver detects link pulses and implements the AutoNegotiation
algorithm
1
0
1
0
1
1
0
1
0
1
1
0
1
0
1
Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
1
0
1
0
1
1
0
1
0
1
Table
Bit Value
1
0
1
0
1
2.3.
1
0
1
0
1
1
0
1
0
1
1
0
1
0
1
1
0
1
0
1
1
0
1
0
1
1
0
1
0
1
1
0
1
0
1
2
1
0
1
1
1
D0
D1
D2
D3
1
3
D4
D5
D6
D7
2-7
1
4