MC33989PEG Freescale Semiconductor, MC33989PEG Datasheet - Page 30

• Manufacturer Part Number: MC33989PEG
• Description: SBC-HS
• Manufacturer: Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
SPI INTERFACE AND REGISTER DESCRIPTION
a read/write bit. The last four bits are Data Send from MCU to SBC, or read back from SBC to MCU.
at the reset value.
Read operation: R/W Bit = 0
Write operation: R/W Bit = 1
Possible reset conditions include:
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33989
Table 7
There is no significance during write operation state of MISO.
During read operation only the final four bits of MISO have a meaning (content of the accessed register).
The following tables describe the SPI register list, and register bit meaning.
Registers reset value is also described along with the reset condition. Reset condition is the condition causing the bit to be set
(1) If Stop mode entered, it is entered without watchdog, no matter the WDSTOP bit.
(E) Debug mode entry point (Step 5 of the Debug mode entering sequence).
(R) Represents transitions to Reset mode due to V DD1 low.
Stop (1)
illustrates a register, an 8-bit SPI. The first three bits are used to identify the internal SBC register address. Bit four is
R
Stop Debug
R
Wake-up
Normal Request
Figure 16. Simplified State Machine in Debug Modes
Stand-by Debug
Table 7. Data Format Description
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Standby
LOGIC COMMANDS AND REGISTERS
A2
A1
A0
R
R
E
WD: Timeout 350 ms
R/W
R
SPI: Standby Debug
SPI: Normal Debug
(3.4 ms) Expired
Reset Counter
D3
D2
E
R
D1
Reset
D0
Normal Debug
Normal
Analog Integrated Circuit Device Data
R
Wake-up
R
Freescale Semiconductor
Sleep