MC33989PEG Freescale Semiconductor, MC33989PEG Datasheet - Page 56

• Manufacturer Part Number: MC33989PEG
• Description: SBC-HS
• Manufacturer: Freescale Semiconductor

TYPICAL APPLICATIONS
SUPPLEMENTAL APPLICATION NOTES
SOFTWARE ASPECTS
Introduction
to control the device. Structure of the Byte: ADR (3 bits) + R/W (1bit) + DATA (4 bits). MSB is sent first. Refer to MC33989
specifications for more details.
How to Enter in Normal Mode After a Power-Up
56
33989
This section describes the MC33989 operation and the microcontroller SPI software routine that has to be executed in order
TX
RX
TEC=128: the node reaches the error passive level
The DC current can be calculated as follows:
Idc= (Time in dominant * peak current of the fault) / total error frame time
Idc= (17+15)*peak current / ((23*15)+1408)=32 / 1753*peak current
Example for CANL2Vbat (peak current = - 240 mA): Idc = 32*(-) 240 / 1753=(-)4.38 mA
Rx is driven only during the glitch occuring on the CAN bus (the dominant time is shorter than a bit time)
Normal request
23 recessive bits: CAN passive error frame
Power-up
Normal
Node sends one dominant bit. As there is still the fault, the TEC is incremented by 8 each time.
Reset
Read WUR ($80)
Write TIM1 =$BX
Write TIM1= $BX
Read IOR ($60)
Read MCR ($00)
Read CAN ($40)
Figure 47. Normal Mode After Power-up
Figure 46. Node is in Bus Off State
TEC reaches 255: the node is BUS OFF
• Clear V2low, Vsuplow flags
• Clear Batfail, Gfail,Wdrst flags
• read CAN/WU flag
• read LX wake-up flag
• Write watchdog
X is the period of the watchdog ex:$00 for 10 ms
• Write watchdog
X is the period of the watchdog ex $00 for 10 ms
note:this register has to be refreshed before the end of the watchdog
period
ALL FLAGS ARE READ
128 occurrences of 11 recessive bits
Analog Integrated Circuit Device Data
Freescale Semiconductor
BUS OFF is recover