MC33989PEG Freescale Semiconductor, MC33989PEG Datasheet - Page 35

• Manufacturer Part Number: MC33989PEG
• Description: SBC-HS
• Manufacturer: Freescale Semiconductor

Table 21. WUR Register
together. See
Table 22. WUR Control Bits
Table 23. WUR Status Bits
Timing Register (TIM1/2)
Table 24. TIM1 Register
Analog Integrated Circuit Device Data
Freescale Semiconductor
Notes: Status bits have two functions. After SBC wake-up, they indicate the wake-up source (Example: L2WU set at 1 if wake-up source is L2
input). After SBC wake and once the WUR has been read, status bits indicates the real time state of the LX inputs (1 mean LX is above
threshold, 0 means that LX input is below threshold).
only if SBC was in Stop mode.
1. TIM1–controls the watchdog timing selection as well as the window or timeout option. TIM1 is selected when bit D3 is 0.
2. TIM2–is used to define the timing for the cyclic sense and forced wake-up function. TIM2 is selected when bit D3 is read
The wake-up inputs can be configured separately, while L0 and L1 are configured together. Bits L2 and L3 are configured
Table 23
This register is composed of two registers:
LCTR3
Reset Condition
If, after a wake-up from LX input, a WD timeout occurs before the first reading of the WUR register, the LXxWU bits are reset. This can occur
Reset Condition
Please see
operation it is not allowed in either TIM1 or TIM2 registers. Please see
Reset Value
Reset Value
x
x
x
x
0
0
1
1
$100B
Status Bit
$101B
WUR
TMI1
L3WU
L2WU
L1WU
L0WU
provides Status bits data.
Table
Table
LCTR2
22.
x
x
x
x
0
1
0
1
24.
W
W
R
R
Wake-up Occurred (Sleep/Stop Modes), Logic State on Lx (Standby/Normal Modes)
LCTR1
0
0
1
1
x
x
x
x
LCTR3
L3WU
D3
D3
—
—
—
0
0
LCTR0
0
1
0
1
x
x
x
x
POR, RST
POR, NR2R, N2R, STB2R, STO2R
LCTR2
L2WU
WDW
High Level Sensitive
Both Level Sensitive
Low Level Sensitive
D2
D2
—
0
0
Inputs Disabled
L0/L1 Config
Description
—
Table
26.
POR, RST
LCTR1
L1WU
WDT1
D1
D1
—
LOGIC COMMANDS AND REGISTERS
0
0
FUNCTIONAL DEVICE OPERATION
High Level Sensitive
Both Level Sensitive
Low Level Sensitive
Inputs Disabled
L2/L3 Config
—
POR, RST
LCTR0
L0WU
WDT0
D0
D0
—
0
0
33989
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