PIC12F1822-E/MF Microchip Technology, PIC12F1822-E/MF Datasheet - Page 310

• Manufacturer Part Number: PIC12F1822-E/MF
• Description: 3.5 KB Flash, 128 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 D
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 12Fr

Specifications of PIC12F1822-E/MF

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-DFN
• Processor Series: PIC12F
• Core: PIC
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC12F/LF1822/PIC16F/LF1823
26.4.2
The following bits are used to configure the EUSART
for Synchronous slave operation:
• SYNC = 1
• CSRC = 0
• SREN = 0 (for transmit); SREN = 1 (for receive)
• CREN = 0 (for transmit); CREN = 1 (for receive)
• SPEN = 1
Setting the SYNC bit of the TXSTA register configures the
device for synchronous operation. Clearing the CSRC bit
of the TXSTA register configures the device as a slave.
Clearing the SREN and CREN bits of the RCSTA register
ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
EUSART.
26.4.2.1
The operation of the Synchronous Master and Slave
modes
“Synchronous Master
case of the Sleep mode.
TABLE 26-9:
DS41413B-page 310
BAUDCON
INTCON
PIE1
PIR1
RCSTA
TRISA
TRISC
TXREG
TXSTA
Legend:
Note 1:
Name
(2)
2:
*
are
— = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission.
Page provides register information.
PIC12F/LF1822 only.
PIC16F/LF1823 only.
SYNCHRONOUS SLAVE MODE
EUSART Synchronous Slave
Transmit
TMR1GIE
TMR1GIF
ABDOVF
SPEN
CSRC
identical
SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE
TRANSMISSION
Bit 7
GIE
—
—
Transmission”), except in the
RCIDL
PEIE
ADIE
ADIF
(see
Bit 6
RX9
TX9
—
—
Section 26.4.1.3
TRISA5
TMR0IE
TRISC5
SREN
TXEN
RCIE
RCIF
Bit 5
—
EUSART Transmit Data Register
(1)
TRISA4
Preliminary
TRISC4
CREN
SYNC
SCKP
Bit 4
INTE
TXIE
TXIF
(1)
ADDEN
TRISA3
TRISC3
SENDB
BRG16
SSPIE
SSPIF
IOCIE
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
1.
2.
3.
4.
5.
26.4.2.2
1.
2.
3.
4.
5.
6.
7.
8.
Bit 3
The first character will immediately transfer to
the TSR register and transmit.
The second word will remain in TXREG register.
The TXIF bit will not be set.
After the first character has been shifted out of
TSR, the TXREG register will transfer the second
character to the TSR and the TXIF bit will now be
set.
If the PEIE and TXIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
Set the SYNC and SPEN bits and clear the
CSRC bit.
Clear the ANSEL bit for the CK pin (if applicable).
Clear the CREN and SREN bits.
If interrupts are desired, set the TXIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
If 9-bit transmission is desired, set the TX9 bit.
Enable transmission by setting the TXEN bit.
If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
Start
Significant 8 bits to the TXREG register.
TMR0IF
CCP1IE
CCP1IF
TRISA2
TRISC2
BRGH
FERR
transmission
Bit 2
—
Synchronous Slave Transmission
Set-up:
TMR2IE
TMR2IF
TRISC1
TRISA1
OERR
TRMT
WUE
Bit 1
INTF
 2010 Microchip Technology Inc.
by
writing
TMR1IE
TMR1IF
TRISC0
ABDEN
TRISA0
IOCIF
RX9D
TX9D
Bit 0
the
Register
on Page
287*
Least
296
101
102
105
295
124
128
294