PIC12F1822-E/MF Microchip Technology, PIC12F1822-E/MF Datasheet - Page 38

• Manufacturer Part Number: PIC12F1822-E/MF
• Description: 3.5 KB Flash, 128 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 D
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 12Fr

Specifications of PIC12F1822-E/MF

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-DFN
• Processor Series: PIC12F
• Core: PIC
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC12F/LF1822/PIC16F/LF1823
TABLE 3-8:
DS41413B-page 38
380h
381h
382h
383h
384h
385h
386h
387h
388h
389h
38Ah
38Bh
38Ch
38Dh
38Eh
38Fh
390h
391h
392h
393h
394h
395h
396h
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
39Fh
Legend:
Note
Address
Bank 7
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
1: These registers can be addressed from any bank.
2: PIC16F/LF1823 only.
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
—
—
—
—
IOCAP
IOCAN
IOCAF
—
—
—
—
—
—
CLKRCON
—
MDCON
MDSRC
MDCARL
MDCARH
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Name
Shaded locations are unimplemented, read as ‘0’.
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
Program Counter (PC) Least Significant Byte
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
Working Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
MDMSODIS
MDCHODIS MDCHPOL MDCHSYNC
MDCLODIS
CLKREN
MDEN
Bit 7
GIE
—
—
—
—
—
—
Write Buffer for the upper 7 bits of the Program Counter
MDCLPOL
CLKROE
MDOE
Bit 6
PEIE
—
—
—
—
—
—
MDCLSYNC
CLKRSLR
TMR0IE
IOCAP5
IOCAN5
IOCAF5
MDSLR
Bit 5
—
—
—
Preliminary
MDOPOL
IOCAP4
IOCAN4
IOCAF4
INTE
Bit 4
TO
—
—
—
CLKRDC<1:0>
IOCAP3
IOCAN3
IOCAF3
MDOUT
IOCIE
Bit 3
PD
BSR<4:0>
TMR0IF
IOCAP2
IOCAN2
IOCAF2
Bit 2
—
Z
MDMS<3:0>
MDCH<3:0>
MDCL<3:0>
CLKRDIV<2:0>
IOCAN1
IOCAP1
IOCAF1
Bit 1
INTF
 2010 Microchip Technology Inc.
DC
—
IOCAP0
IOCAN0
IOCAF0
MDBIT
IOCIF
Bit 0
C
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
--00 0000 --00 0000
--00 0000 --00 0000
--00 0000 --00 0000
0011 0000 0011 0000
0010 ---0 0010 ---0
x--- xxxx u--- uuuu
xxx- xxxx uuu- uuuu
xxx- xxxx uuu- uuuu
POR, BOR
Value on
—
—
—
—
—
—
—
—
—
—
—
—
Value on all
Resets
other
—
—
—
—
—
—
—
—
—
—
—
—