PIC12F1822-E/MF Microchip Technology, PIC12F1822-E/MF Datasheet - Page 400

• Manufacturer Part Number: PIC12F1822-E/MF
• Description: 3.5 KB Flash, 128 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 D
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 12Fr

Specifications of PIC12F1822-E/MF

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-DFN
• Processor Series: PIC12F
• Core: PIC
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC12F/LF1822/PIC16F/LF1823
Timer2/4/6
Timers
Timing Diagrams
DS41413B-page 400
Associated registers.................................................. 191
Associated registers.................................................. 191
Timer1
Timer2
A/D Conversion ......................................................... 364
A/D Conversion (Sleep Mode) .................................. 364
Acknowledge Sequence ........................................... 271
Asynchronous Reception .......................................... 292
Asynchronous Transmission ..................................... 288
Asynchronous Transmission (Back to Back) ............ 288
Auto Wake-up Bit (WUE) During Normal Operation . 304
Auto Wake-up Bit (WUE) During Sleep .................... 304
Automatic Baud Rate Calibration .............................. 302
Baud Rate Generator with Clock Arbitration ............. 264
BRG Reset Due to SDA Arbitration During Start
Brown-out Reset (BOR) ............................................ 360
Brown-out Reset Situations ........................................ 79
Bus Collision During a Repeated Start Condition
Bus Collision During a Repeated Start Condition
Bus Collision During a Start Condition (SCL = 0) ..... 275
Bus Collision During a Stop Condition (Case 1) ....... 277
Bus Collision During a Stop Condition (Case 2) ....... 277
Bus Collision During Start Condition (SDA only) ...... 274
Bus Collision for Transmit and Acknowledge............ 273
CLKOUT and I/O....................................................... 358
Clock Synchronization .............................................. 261
Clock Timing ............................................................. 356
Comparator Output ................................................... 163
Enhanced Capture/Compare/PWM (ECCP) ............. 362
Fail-Safe Clock Monitor (FSCM) ................................. 68
First Start Bit Timing ................................................. 265
Full-Bridge PWM Output ........................................... 217
Half-Bridge PWM Output .................................. 215, 222
I
I
I
I
I
INT Pin Interrupt.......................................................... 89
Internal Oscillator Switch Timing................................. 63
PWM Auto-shutdown ................................................ 221
PWM Direction Change ............................................ 218
PWM Direction Change at Near 100% Duty Cycle ... 219
PWM Output (Active-High)........................................ 213
PWM Output (Active-Low) ........................................ 214
Repeat Start Condition.............................................. 266
Reset Start-up Sequence............................................ 81
Reset, WDT, OST and Power-up Timer ................... 359
Send Break Character Sequence ............................. 305
SPI Master Mode (CKE = 1, SMP = 1) ..................... 367
SPI Mode (Master Mode) .......................................... 238
SPI Slave Mode (CKE = 0) ....................................... 368
SPI Slave Mode (CKE = 1) ....................................... 368
Synchronous Reception (Master Mode, SREN) ....... 309
Synchronous Transmission....................................... 307
2
2
2
2
2
C Bus Data ............................................................. 370
C Bus Start/Stop Bits.............................................. 369
C Master Mode (7 or 10-Bit Transmission) ............ 268
C Master Mode (7-Bit Reception) ........................... 270
C Stop Condition Receive or Transmit Mode ......... 272
T1CON.............................................................. 185
T1GCON ........................................................... 186
T2CON.............................................................. 190
Condition........................................................... 275
(Case 1) ............................................................ 276
(Case 2) ............................................................ 276
Firmware Restart .............................................. 220
Preliminary
Timing Diagrams and Specifications
Timing Parameter Symbology .......................................... 355
Timing Requirements
TMR0 Register.................................................................... 31
TMR1H Register ................................................................. 31
TMR1L Register.................................................................. 31
TMR2 Register.................................................................... 31
TRIS.................................................................................. 340
TRISA Register........................................................... 32, 124
TRISC Register........................................................... 32, 128
Two-Speed Clock Start-up Mode........................................ 65
TXREG ............................................................................. 287
TXREG Register ................................................................. 34
TXSTA Register.......................................................... 34, 294
U
USART
V
V
W
Wake-up on Break ............................................................ 303
Wake-up Using Interrupts ................................................... 98
Watchdog Timer (WDT)...................................................... 80
WCOL ....................................................... 264, 267, 269, 271
WCOL Status Flag.................................... 264, 267, 269, 271
WDTCON Register ........................................................... 103
WPUB Register................................................................. 126
WPUC Register ................................................................ 129
Write Protection .................................................................. 53
WWW Address ................................................................. 401
WWW, On-Line Support ..................................................... 10
REF
Synchronous Transmission (Through TXEN) ........... 307
Timer0 and Timer1 External Clock ........................... 361
Timer1 Incrementing Edge ....................................... 181
Two Speed Start-up.................................................... 66
USART Synchronous Receive (Master/Slave) ......... 366
USART Synchronous Transmission (Master/Slave). 366
Wake-up from Interrupt............................................... 98
PLL Clock ................................................................. 357
I
SPI Mode .................................................................. 369
BRGH Bit .................................................................. 297
Synchronous Master Mode
Modes ....................................................................... 102
Specifications ........................................................... 361
. S
2
C Bus Data............................................................. 371
EE
Requirements, Synchronous Receive .............. 366
Requirements, Synchronous Transmission...... 366
Timing Diagram, Synchronous Receive ........... 366
Timing Diagram, Synchronous Transmission... 366
ADC Reference Voltage
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