PIC16F1527-E/MR Microchip Technology, PIC16F1527-E/MR Datasheet - Page 262

• Manufacturer Part Number: PIC16F1527-E/MR
• Description: 64-pin, 28KB Flash, 1536B RAM, 10-bit ADC, 10xCCP, 2xSPI, 2xMI2C, 2xEUSART, 2.3V
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1527-E/MR

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 28KB (16K x 14)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 5.5 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-VFQFN Exposed Pad
• Core: PIC
• Processor Series: PIC16F
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Data Ram Size: 1536 B
• Number Of Programmable I/os: 54
• Operating Supply Voltage: 2.3 V to 5.5 V
• Mounting Style: SMD/SMT
• Interface Type: SPI, I2C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16(L)F1526/27
22.1.2.9
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Get the received 8 Least Significant data bits
11. If an overrun occurred, clear the OERR flag by
DS41458B-page 262
Initialize the SPxBRGH:SPxBRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see
Baud Rate Generator (BRG)”
Set the RXx/DTx and TXx/CKx TRIS controls to
‘1’.
Enable the serial port by setting the SPEN bit
and the RXx/DTx pin TRIS bit. The SYNC bit
must be clear for asynchronous operation.
If interrupts are desired, set the RCxIE interrupt
enable bit and set the GIE and PEIE bits of the
INTCON register.
If 9-bit reception is desired, set the RX9 bit.
Set the DTRXP if inverted receive polarity is
desired.
Enable reception by setting the CREN bit.
The RCxIF interrupt flag bit will be set when a
character is transferred from the RSR to the
receive buffer. An interrupt will be generated if
the RCxIE interrupt enable bit was also set.
Read the RCxSTA register to get the error flags
and, if 9-bit data reception is enabled, the ninth
data bit.
from the receive buffer by reading the RCxREG
register.
clearing the CREN receiver enable bit.
Asynchronous Reception Set-up:
Section 22.4 “EUSART
).
Preliminary
22.1.2.10
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Read the RCxSTA register to get the error flags.
11. Get the received 8 Least Significant data bits
12. If an overrun occurred, clear the OERR flag by
13. If the device has been addressed, clear the
Initialize the SPxBRGH, SPxBRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see
Baud Rate Generator (BRG)”
Set the RXx/DTx and TXx/CKx TRIS controls to
‘1’.
Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
If interrupts are desired, set the RCxIE interrupt
enable bit and set the GIE and PEIE bits of the
INTCON register.
Enable 9-bit reception by setting the RX9 bit.
Enable address detection by setting the ADDEN
bit.
Set the DTRXP if inverted receive polarity is
desired.
Enable reception by setting the CREN bit.
The RCxIF interrupt flag bit will be set when a
character with the ninth bit set is transferred
from the RSR to the receive buffer. An interrupt
will be generated if the RCxIE interrupt enable
bit was also set.
The ninth data bit will always be set.
from the receive buffer by reading the RCxREG
register. Software determines if this is the
device’s address.
clearing the CREN receiver enable bit.
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.
9-bit Address Detection Mode Set-up
 2011 Microchip Technology Inc.
Section 22.4 “EUSART
).