PIC16F1527-E/MR Microchip Technology, PIC16F1527-E/MR Datasheet - Page 86

• Manufacturer Part Number: PIC16F1527-E/MR
• Description: 64-pin, 28KB Flash, 1536B RAM, 10-bit ADC, 10xCCP, 2xSPI, 2xMI2C, 2xEUSART, 2.3V
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1527-E/MR

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 28KB (16K x 14)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 5.5 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-VFQFN Exposed Pad
• Core: PIC
• Processor Series: PIC16F
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Data Ram Size: 1536 B
• Number Of Programmable I/os: 54
• Operating Supply Voltage: 2.3 V to 5.5 V
• Mounting Style: SMD/SMT
• Interface Type: SPI, I2C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16(L)F1526/27
7.6.7
The PIR2 register contains the interrupt flag bits, as
shown in
REGISTER 7-7:
DS41458B-page 86
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W-0/0
OSFIF
Register
PIR2 REGISTER
OSFIF: Oscillator Fail Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
TMR5GIF: Timer5 Gate Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
TMR3GIF: Timer3 Gate Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
Unimplemented: Read as ‘0’
BCL1IF: MSSP1 Bus Collision Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
TMR10IF: Timer10 to PR10 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
TMR8IF: Timer8 to PR8 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
CCP2IF: CCP2 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
TMR5GIF
7-7.
R/W-0/0
PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
TMR3GIF
R/W-0/0
U-0
Preliminary
—
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
R/W-0/0
BCL1IF
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
TMR10IF
R/W-0/0
software
 2011 Microchip Technology Inc.
R/W-0/0
TMR8IF
should
ensure
R/W-0/0
CCP2IF
bit 0
the