PIC16F1527-E/MR Microchip Technology, PIC16F1527-E/MR Datasheet - Page 330

• Manufacturer Part Number: PIC16F1527-E/MR
• Description: 64-pin, 28KB Flash, 1536B RAM, 10-bit ADC, 10xCCP, 2xSPI, 2xMI2C, 2xEUSART, 2.3V
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1527-E/MR

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 28KB (16K x 14)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 5.5 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-VFQFN Exposed Pad
• Core: PIC
• Processor Series: PIC16F
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Data Ram Size: 1536 B
• Number Of Programmable I/os: 54
• Operating Supply Voltage: 2.3 V to 5.5 V
• Mounting Style: SMD/SMT
• Interface Type: SPI, I2C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16(L)F1526/27
TABLE 25-13: I
DS41458B-page 330
Note 1:
Param.
SP100* T
SP101* T
SP102* T
SP103* T
SP106* T
SP107* T
SP109* T
SP110* T
SP111
No.
2:
*
These parameters are characterized but not tested.
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions.
A Fast mode (400 kHz) I
the requirement T
not stretch the low period of the SCLx signal. If such a device does stretch the low period of the SCLx sig-
nal, it must output the next data bit to the SDAx line T
to the Standard mode I
C
Symbol
SU
AA
R
HIGH
LOW
F
HD
BUF
B
:
:
DAT
DAT
2
C™ BUS DATA REQUIREMENTS
Clock high time
Clock low time
SDAx and SCLx
rise time
SDAx and SCLx fall
time
Data input hold time 100 kHz mode
Data input setup
time
Output valid from
clock
Bus free time
Bus capacitive loading
SU
:
DAT
Characteristic
2
C bus specification), before the SCLx line is released.
2
 250 ns must then be met. This will automatically be the case if the device does
C
™
bus device can be used in a Standard mode (100 kHz) I
100 kHz mode
400 kHz mode
SSP module
100 kHz mode
400 kHz mode
SSP module
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
Preliminary
20 + 0.1C
20 + 0.1C
1.5T
1.5T
R
Min.
250
100
4.0
0.6
4.7
1.3
4.7
1.3
max. + T
—
—
—
—
—
0
0
CY
CY
B
B
SU
Max.
1000
3500
300
250
250
0.9
400
—
—
—
—
—
—
—
—
—
—
—
—
:
DAT
= 1000 + 250 = 1250 ns (according
Units
 s
 s
 s
 s
 s
 s
 s
pF
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
 2011 Microchip Technology Inc.
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
C
10-400 pF
C
10-400 pF
(Note 2)
(Note 1)
Time the bus must be free
before a new transmission
can start
B
B
is specified to be from
is specified to be from
2
Conditions
C bus system, but