PIC18F96J60T-I/PF Microchip Technology, PIC18F96J60T-I/PF Datasheet - Page 159

• Manufacturer Part Number: PIC18F96J60T-I/PF
• Description: 64KB Flash, 12KB RAM, 10BASE-T Ethernet 100 TQFP 14x14x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F96J60T-I/PF

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164333 - MODULE SKT FOR PM3 100QFPAC162064 - HEADER INTFC MPLABICD2 64/80/100
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

10.9
PORTH is an 8-bit wide, bidirectional I/O port; it is fully
implemented on 80-pin and 100-pin devices. The
corresponding Data Direction register is TRISH. Set-
ting a TRISH bit (= 1) will make the corresponding
PORTH pin an input (i.e., put the corresponding output
driver in a high-impedance mode). Clearing a TRISH
bit (= 0) will make the corresponding PORTH pin an
output (i.e., put the contents of the output latch on the
selected pin). PORTH<3:0> pins are digital only and
tolerate voltages up to 5.5V.
The Output Latch register (LATH) is also memory
mapped. Read-modify-write operations on the LATH
register read and write the latched output value for
PORTH.
All pins on PORTH are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
© 2009 Microchip Technology Inc.
Note:
PORTH, LATH and
TRISH Registers
PORTH is available only on 80-pin and
100-pin devices.
PIC18F97J60 FAMILY
When the external memory interface is enabled, four of
the PORTH pins function as the high-order address
lines for the interface. The address output from the
interface takes priority over other digital I/O. The
corresponding TRISH bits are also overridden.
PORTH pins, RH4 through RH7, are multiplexed with
analog converter inputs. The operation of these pins as
analog inputs is selected by clearing or setting the
PCFG3:PCFG0 control bits in the ADCON1 register.
PORTH can also be configured as the alternate
Enhanced PWM output channels B and C for the
ECCP1 and ECCP3 modules. This is done by clearing
the ECCPMX Configuration bit.
EXAMPLE 10-8:
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVWF
PORTH
LATH
0Fh
ADCON1
0CFh
TRISH
INITIALIZING PORTH
; Initialize PORTH by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Configure PORTH as
; digital I/O
; Value used to
; initialize data
; direction
; Set RH3:RH0 as inputs
; RH5:RH4 as outputs
; RH7:RH6 as inputs
DS39762E-page 159