PIC18F96J60T-I/PF Microchip Technology, PIC18F96J60T-I/PF Datasheet - Page 215

• Manufacturer Part Number: PIC18F96J60T-I/PF
• Description: 64KB Flash, 12KB RAM, 10BASE-T Ethernet 100 TQFP 14x14x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F96J60T-I/PF

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164333 - MODULE SKT FOR PM3 100QFPAC162064 - HEADER INTFC MPLABICD2 64/80/100
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

18.2.1.2
The receive buffer constitutes a circular FIFO buffer
managed
ERXSTH:ERXSTL and ERXNDH:ERXNDL, serve as
pointers to define the buffer’s size and location within
the memory. The byte pointed to by the ERXST pair
and the byte pointed to by the ERXND pair are both
included in the FIFO buffer.
As bytes of data are received from the Ethernet
interface, they are written into the receive buffer
sequentially. However, after the memory pointed to by
the ERXND Pointers is written to, the hardware will
automatically write the next byte of received data to the
memory pointed to by the ERXST pair. As a result, the
receive hardware will never write outside the
boundaries of the FIFO.
The user may program the ERXST and ERXND
Pointers while the receive logic is disabled. The point-
ers must not be modified while the receive logic is
enabled (ERXEN (ECON1<2>) is set).
The buffer hardware uses an Internal Pointer (not
mapped to any user-accessible registers) to determine
where unvalidated incoming data is to be written. When
a packet has been completely received and validated,
FIGURE 18-5:
© 2009 Microchip Technology Inc.
Sets boundary that Internal
Write Pointer cannot advance
beyond. Prevents Internal
Write Pointer from moving
into Packet 1’s data space.
Data being read
out to application.
by
ERXRDPT:
Receive Buffer
ERDPT:
hardware.
PB
CIRCULAR FIFO BUFFER AND THE RELATIONSHIPS OF THE POINTERS
The
PB
PB
(being processed
ERXST
by application)
Packet 2
register
Packet 1
Direction of reading and writing data
(lower to higher buffer addresses)
pairs,
Packet 3
(may contain old data)
Unused Buffer
PIC18F97J60 FAMILY
the read-only ERXWRPTH:ERXWRPTL registers are
updated with the Internal Pointer’s value. Thus, the
ERXWRPT registers define the general area in the
receive buffer where data is currently being written. This
makes it useful for determining how much free space is
available within the FIFO.
The ERXRDPT registers define a location within the
FIFO where the receive hardware is forbidden to write to.
In normal operation, the receive hardware will write data
up to, but not including, the memory pointed to by the
ERXRDPT registers. If the FIFO fills up with data and
new data continues to arrive, the hardware will not over-
write the previously received data. Instead, the incoming
data will be thrown away and the old data will be
preserved. In order to continuously receive new data, the
application must periodically advance this pointer when-
ever it finishes processing some, or all, of the old
received data.
An example of how the Receive Buffer Pointers and
packet data are related in the circular buffer scheme is
shown in Figure 18-5. Note that while four packets are
shown in this example, the actual number of packets
may be greater or lesser.
(currently being
received)
Packet 4
ERXND
PB
PB: Packet Boundary, as defined by
the Next Packet Pointers that precede
each packet.
ERXWRPT:
Shows the end of
the last complete
received packet.
Internal Write Hardware Pointer
points to the buffer
location being written
(packet data is still
being received).
DS39762E-page 215