PIC18F96J60T-I/PF Microchip Technology, PIC18F96J60T-I/PF Datasheet - Page 163

• Manufacturer Part Number: PIC18F96J60T-I/PF
• Description: 64KB Flash, 12KB RAM, 10BASE-T Ethernet 100 TQFP 14x14x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F96J60T-I/PF

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164333 - MODULE SKT FOR PM3 100QFPAC162064 - HEADER INTFC MPLABICD2 64/80/100
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

10.11 Parallel Slave Port
PORTD can also function as an 8-bit wide, Parallel
Slave Port, or microprocessor port, when control bit,
PSPMODE (PSPCON<4>), is set. It is asynchronously
readable and writable by the external world through the
RD control input pin, RE0/AD8/RD/P2D and WR
control input pin, RE1/AD9//WR/P2C.
The PSP can directly interface to an 8-bit micro-
processor data bus. The external microprocessor can
read or write the PORTD latch as an 8-bit latch. Setting
bit, PSPMODE, enables port pin RE0/AD8/RD/P2D to
be the RD input, RE1/AD9//WR/P2C to be the WR
input and RE2/AD10//CS/P2B to be the CS (Chip
Select) input. For this functionality, the corresponding
data direction bits of the TRISE register (TRISE<2:0>)
must be configured as inputs (set).
A write to the PSP occurs when both the CS and WR
lines are first detected low and ends when either are
detected high. The PSPIF and IBF flag bits are both set
when the write ends.
A read from the PSP occurs when both the CS and RD
lines are first detected low. The data in PORTD is read
out and the OBF bit is set. If the user writes new data
to PORTD to set OBF, the data is immediately read out;
however, the OBF bit is not set.
When either the CS or RD lines is detected high, the
PORTD pins return to the input state and the PSPIF bit
is set. User applications should wait for PSPIF to be set
before servicing the PSP. When this happens, the IBF
and OBF bits can be polled and the appropriate action
taken.
The timing for the control signals in Write and Read
modes is shown in Figure 10-3 and Figure 10-4,
respectively.
© 2009 Microchip Technology Inc.
Note:
Note:
The Parallel Slave Port is available only in
Microcontroller mode.
The Parallel Slave Port is only implemented
in 100-pin devices.
PIC18F97J60 FAMILY
FIGURE 10-2:
One bit of PORTD
Data Bus
Set Interrupt Flag
PSPIF (PIR1<7>)
WR LATD
or PORTD
RD PORTD
RD LATD
Data Latch
TRIS Latch
D
Q
CK
EN
EN
Q
D
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE PORT)
Chip Select
DS39762E-page 163
Read
Write
TTL
TTL
TTL
TTL
RD
CS
WR
RDx
pin