PIC18F96J60T-I/PF Microchip Technology, PIC18F96J60T-I/PF Datasheet - Page 259

• Manufacturer Part Number: PIC18F96J60T-I/PF
• Description: 64KB Flash, 12KB RAM, 10BASE-T Ethernet 100 TQFP 14x14x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F96J60T-I/PF

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164333 - MODULE SKT FOR PM3 100QFPAC162064 - HEADER INTFC MPLABICD2 64/80/100
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

19.0
19.1
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I
The I
hardware:
• Master mode
• Multi-Master mode
• Slave mode
The 64-pin and 80-pin devices of the PIC18F97J60
family have one MSSP module, designated as MSSP1.
The 100-pin devices have two MSSP modules, desig-
nated as MSSP1 and MSSP2. Each module operates
independently of the other.
19.2
Each MSSP module has three associated control
registers. These include a status register (SSPxSTAT)
and two control registers (SSPxCON1 and SSPxCON2).
The use of these registers and their individual configura-
tion bits differ significantly depending on whether the
MSSP module is operating in SPI or I
Additional details are provided under the individual
sections.
© 2009 Microchip Technology Inc.
- Full Master mode
- Slave mode (with general address call)
Note:
Note:
2
C interface supports the following modes in
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
Master SSP (MSSP) Module
Overview
Control Registers
Throughout this section, generic refer-
ences to an MSSP module in any of its
operating modes may be interpreted as
being equally applicable to MSSP1 or
MSSP2. Register names and module I/O
signals use the generic designator ‘x’ to
indicate the use of a numeral to distinguish
a
Control bit names are not individuated.
In devices with more than one MSSP
module, it is very important to pay close
attention to the SSPxCON register names.
SSP1CON1 and
different operational aspects of the same
module,
SSP2CON1 control the same features for
two different modules.
particular
while
2
module when required.
C™)
SSP1CON2 control
SSP1CON1
2
C mode.
and
PIC18F97J60 FAMILY
19.3
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes
communication, typically three pins are used:
• Serial Data Out (SDOx) – RC5/SDO1 (or
• Serial Data In (SDIx) – RC4/SDI1/SDA1 (or
• Serial Clock (SCKx) – RC3/SCK1/SCL1 (or
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SSx) – RF7/SS1 (or RD7/SS2 for
Figure 19-1 shows the block diagram of the MSSP
module when operating in SPI mode.
FIGURE 19-1:
RD4/SDO2 for 100-pin devices)
RD5/SDI2/SDA2 for 100-pin devices)
RD6/SCK2/SCL2 for 100-pin devices)
100-pin devices)
SCKx
SDOx
SDIx
SSx
SPI Mode
of
SPI
Read
SSx Control
are
Select
SMP:CKE
Edge
bit 0
Select
Edge
MSSP BLOCK DIAGRAM
(SPI MODE)
Enable
SSPxBUF reg
Data to TXx/RXx in SSPxSR
TRIS bit
SSPM3:SSPM0
2
SSPxSR reg
supported.
Clock Select
4
2
DS39762E-page 259
(
Prescaler
4, 16, 64
TMR2 Output
Write
To
Clock
Shift
Internal
Data Bus
2
accomplish
T
OSC
)