PIC18F96J65T-I/PF Microchip Technology, PIC18F96J65T-I/PF Datasheet - Page 376

• Manufacturer Part Number: PIC18F96J65T-I/PF
• Description: 96KB Flash, 12KB RAM, 10BASE-T Ethernet 100 TQFP 14x14x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F96J65T-I/PF

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 96KB (48K x 16)
• Program Memory Type: FLASH
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F97J60 FAMILY
BTFSC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39762E-page 376
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
If FLAG<1>
If FLAG<1>
No
No
No
Q1
Q1
Q1
PC
PC
Bit Test File, Skip if Clear
BTFSC f, b {,a}
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
skip if (f<b>) = 0
None
If bit ‘b’ in register ‘f’ is ‘0’, then the next
instruction is skipped. If bit ‘b’ is ‘0’, then
the next instruction fetched during the
current instruction execution is discarded
and a NOP is executed instead, making
this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction set
is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1(2)
Note: 3 cycles if skip and followed
register ‘f’
HERE
FALSE
TRUE
operation
operation
operation
Read
1011
No
No
No
=
=
=
=
=
Q2
Q2
Q2
by a 2-word instruction.
address (HERE)
0;
address (TRUE)
1;
address (FALSE)
BTFSC
:
:
bbba
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
FLAG, 1, 0
ffff
operation
operation
operation
operation
No
No
No
No
Q4
Q4
Q4
ffff
BTFSS
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
If FLAG<1>
If FLAG<1>
No
No
No
Q1
Q1
Q1
PC
PC
Bit Test File, Skip if Set
BTFSS f, b {,a}
0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0,1]
skip if (f<b>) = 1
None
If bit ‘b’ in register ‘f’ is ‘1’, then the next
instruction is skipped. If bit ‘b’ is ‘1’, then
the next instruction fetched during the
current instruction execution is discarded
and a NOP is executed instead, making
this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1(2)
Note:
register ‘f’
HERE
FALSE
TRUE
operation
operation
operation
Read
1010
No
No
No
=
=
=
=
=
Q2
Q2
Q2
© 2009 Microchip Technology Inc.
address (HERE)
0;
address (FALSE)
1;
address (TRUE)
3 cycles if skip and followed
by a 2-word instruction.
BTFSS
:
:
bbba
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
FLAG, 1, 0
ffff
operation
operation
operation
operation
No
No
No
No
Q4
Q4
Q4
ffff