PIC18F96J65T-I/PF Microchip Technology, PIC18F96J65T-I/PF Datasheet - Page 399

• Manufacturer Part Number: PIC18F96J65T-I/PF
• Description: 96KB Flash, 12KB RAM, 10BASE-T Ethernet 100 TQFP 14x14x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F96J65T-I/PF

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 96KB (48K x 16)
• Program Memory Type: FLASH
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

SUBLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example 1:
Example 2:
Example 3:
© 2009 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
W
C
W
C
Z
N
W
C
W
C
Z
N
W
C
W
C
Z
N
Q1
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
literal ‘k’
Subtract W from Literal
SUBLW k
0 ≤ k ≤ 255
k – (W) → W
N, OV, C, DC, Z
W is subtracted from the eight-bit
literal ‘k’. The result is placed in W.
1
1
SUBLW
SUBLW
SUBLW
Read
Q2
0000
01h
?
01h
1
0
0
02h
?
00h
1
1
0
03h
?
FFh
0
0
1
; result is positive
; result is zero
; result is negative
; (2’s complement)
02h
02h
02h
1000
Process
Data
Q3
kkkk
Write to
Q4
W
kkkk
PIC18F97J60 FAMILY
SUBWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example 1:
Example 2:
Example 3:
Q Cycle Activity:
Before Instruction
After Instruction
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
REG
W
C
REG
W
C
Z
N
REG
W
C
REG
W
C
Z
N
REG
W
C
REG
W
C
Z
N
Q1
Subtract W from f
SUBWF
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f) – (W) → dest
N, OV, C, DC, Z
Subtract W from register ‘f’ (2’s
complement method). If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the result
is stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
register ‘f’
0101
SUBWF
SUBWF
SUBWF
Read
Q2
3
2
?
1
2
1
0
0
2
2
?
2
0
1
1
0
1
2
?
FFh ;(2’s complement)
2
0
0
1
f {,d {,a}}
; result is positive
; result is zero
; result is negative
11da
REG, 1, 0
REG, 0, 0
REG, 1, 0
Process
Data
Q3
DS39762E-page 399
ffff
destination
Write to
Q4
ffff