PIC18F96J65T-I/PF Microchip Technology, PIC18F96J65T-I/PF Datasheet - Page 473

• Manufacturer Part Number: PIC18F96J65T-I/PF
• Description: 96KB Flash, 12KB RAM, 10BASE-T Ethernet 100 TQFP 14x14x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F96J65T-I/PF

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 96KB (48K x 16)
• Program Memory Type: FLASH
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

RESET ............................................................................. 393
Reset .................................................................................. 57
Resets .............................................................................. 349
RETFIE ............................................................................ 394
RETLW ............................................................................ 394
RETURN .......................................................................... 395
Return Address Stack ........................................................ 75
Return Stack Pointer (STKPTR) ........................................ 76
Revision History ............................................................... 463
RLCF ................................................................................ 395
RLNCF ............................................................................. 396
RRCF ............................................................................... 396
RRNCF ............................................................................ 397
S
SCKx ................................................................................ 259
SDIx ................................................................................. 259
SDOx ............................................................................... 259
SEC_IDLE Mode ................................................................ 54
SEC_RUN Mode ................................................................ 50
Serial Clock, SCKx ........................................................... 259
Serial Data In (SDIx) ........................................................ 259
Serial Data Out (SDOx) ................................................... 259
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 397
Slave Select (SSx) ........................................................... 259
SLEEP ............................................................................. 398
Sleep
Software Simulator (MPLAB SIM) .................................... 415
Special Event Trigger. See Compare (ECCP Module).
© 2009 Microchip Technology Inc.
PSPCON (Parallel Slave Port Control) .................... 164
RCON (Reset Control) ....................................... 58, 137
RCSTAx (Receive Status and Control x) ................. 307
SSPxCON1 (MSSPx Control 1, I
SSPxCON1 (MSSPx Control 1, SPI Mode) ............. 261
SSPxCON2 (MSSPx Control 2, I
SSPxCON2 (MSSPx Control 2, I
SSPxSTAT (MSSPx Status, I
SSPxSTAT (MSSPx Status, SPI Mode) .................. 260
STATUS ..................................................................... 91
STKPTR (Stack Pointer) ............................................ 76
T0CON (Timer0 Control) .......................................... 167
T1CON (Timer1 Control) .......................................... 171
T2CON (Timer2 Control) .......................................... 177
T3CON (Timer3 Control) .......................................... 179
T4CON (Timer4 Control) .......................................... 183
TXSTAx (Transmit Status and Control x) ................. 306
WDTCON (Watchdog Timer Control) ...................... 357
Brown-out Reset (BOR) ............................................. 57
Configuration Mismatch (CM) .................................... 57
MCLR Reset, During Power-Managed Modes ........... 57
MCLR Reset, Normal Operation ................................ 57
Power-on Reset (POR) .............................................. 57
Reset Instruction ........................................................ 57
Stack Full Reset ......................................................... 57
Stack Underflow Reset .............................................. 57
State of Registers ...................................................... 62
Watchdog Timer (WDT) Reset ................................... 57
Brown-out Reset (BOR) ........................................... 349
Oscillator Start-up Timer (OST) ............................... 349
Power-on Reset (POR) ............................................ 349
Power-up Timer (PWRT) ......................................... 349
Stack Full/Underflow .................................................. 77
OSC1 and OSC2 Pin States ...................................... 48
2
C Mode) ................... 270
2
2
2
C Mode) .............. 271
C Master Mode) .. 272
C Slave Mode) .... 273
PIC18F97J60 FAMILY
Special Features of the CPU ........................................... 349
Special Function Registers
SPI Mode (MSSP)
SSPOV ............................................................................ 294
SSPOV Status Flag ......................................................... 294
SSPSTAT Register
SSPxSTAT Register
SSx .................................................................................. 259
SUBFSR .......................................................................... 409
SUBFWB ......................................................................... 398
SUBLW ............................................................................ 399
SUBULNK ........................................................................ 409
SUBWF ............................................................................ 399
SUBWFB ......................................................................... 400
SWAPF ............................................................................ 400
T
Table Pointer Operations (table) ...................................... 102
Table Reads/Table Writes ................................................. 77
TBLRD ............................................................................. 401
TBLWT ............................................................................ 402
Timer0 ............................................................................. 167
Timer1 ............................................................................. 171
Ethernet SFRs ........................................................... 84
Associated Registers ............................................... 268
Bus Mode Compatibility ........................................... 267
Clock Speed and Module Interactions ..................... 267
Effects of a Reset .................................................... 267
Enabling SPI I/O ...................................................... 263
Master Mode ............................................................ 264
Master/Slave Connection ........................................ 263
Operation ................................................................. 262
Operation in Power-Managed Modes ...................... 267
Serial Clock ............................................................. 259
Serial Data In ........................................................... 259
Serial Data Out ........................................................ 259
Slave Mode .............................................................. 265
Slave Select ............................................................. 259
Slave Select Synchronization .................................. 265
SPI Clock ................................................................. 264
Typical Connection .................................................. 263
R/W Bit .................................................................... 276
R/W Bit .................................................................... 274
Associated Registers ............................................... 169
Clock Source Select (T0CS Bit) .............................. 168
Operation ................................................................. 168
Overflow Interrupt .................................................... 169
Prescaler ................................................................. 169
Prescaler Assignment (PSA Bit) .............................. 169
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 169
Prescaler, Switching Assignment ............................ 169
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 168
Source Edge Select (T0SE Bit) ............................... 168
16-Bit Read/Write Mode .......................................... 173
Associated Registers ............................................... 175
Considerations in Asynchronous Counter Mode ..... 174
Interrupt ................................................................... 174
Operation ................................................................. 172
Oscillator .......................................................... 171, 173
Overflow Interrupt .................................................... 171
Resetting, Using the ECCPx Special Event Trigger 174
Special Event Trigger (ECCP) ................................. 196
Layout Considerations ..................................... 173
DS39762E-page 473