PIC24FJ64GA106-I/MR Microchip Technology, PIC24FJ64GA106-I/MR Datasheet - Page 181

• Manufacturer Part Number: PIC24FJ64GA106-I/MR
• Description: 16-bit, 16 MIPS, 64KB Flash, 16Kb RAM, 84 I/O, NanoWatt 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ64GA106-I/MR

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (22K x 24)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Processor Series: PIC24FJ256GA110
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

REGISTER 15-2:
REGISTER 15-3:
 2010 Microchip Technology Inc.
bit 4-2
bit 1-0
Note 1:
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-2
bit 1
bit 0
FRMEN
R/W-0
U-0
—
2:
3:
4:
If DISSCK = 0, SCKx must be configured to an available RPn pin (or to ASCK1 for SPI1). See
Section 10.4 “Peripheral Pin Select”
If DISSDO = 0, SDOx must be configured to an available RPn pin. See
Select”
The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed
SPI modes (FRMEN = 1).
If SSEN = 1, SSx must be configured to an available RPn pin. See
for more information.
SPRE<2:0>: Secondary Prescale bits (Master mode)
111 = Secondary prescale 1:1
110 = Secondary prescale 2:1
...
000 = Secondary prescale 8:1
PPRE<1:0>: Primary Prescale bits (Master mode)
11 = Primary prescale 1:1
10 = Primary prescale 4:1
01 = Primary prescale 16:1
00 = Primary prescale 64:1
FRMEN: Framed SPIx Support bit
1 = Framed SPIx support enabled
0 = Framed SPIx support disabled
SPIFSD: Frame Sync Pulse Direction Control on SSx Pin bit
1 = Frame sync pulse input (slave)
0 = Frame sync pulse output (master)
SPIFPOL: Frame Sync Pulse Polarity bit (Frame mode only)
1 = Frame sync pulse is active-high
0 = Frame sync pulse is active-low
Unimplemented: Read as ‘0’
SPIFE: Frame Sync Pulse Edge Select bit
1 = Frame sync pulse coincides with first bit clock
0 = Frame sync pulse precedes first bit clock
SPIBEN: Enhanced Buffer Enable bit
1 = Enhanced Buffer enabled
0 = Enhanced Buffer disabled (Legacy mode)
SPIFSD
R/W-0
for more information.
U-0
—
SPI
SPIxCON2: SPIx CONTROL REGISTER 2
X
CON1: SPIx CONTROL REGISTER 1 (CONTINUED)
W = Writable bit
‘1’ = Bit is set
SPIFPOL
R/W-0
U-0
—
PIC24FJ256GA110 FAMILY
U-0
U-0
—
—
for more information.
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
—
—
Section 10.4 “Peripheral Pin Select”
U-0
U-0
—
—
Section 10.4 “Peripheral Pin
x = Bit is unknown
SPIFE
R/W-0
U-0
—
DS39905E-page 181
SPIBEN
R/W-0
U-0
—
bit 8
bit 0