PIC24FJ64GA106-I/MR Microchip Technology, PIC24FJ64GA106-I/MR Datasheet - Page 37

• Manufacturer Part Number: PIC24FJ64GA106-I/MR
• Description: 16-bit, 16 MIPS, 64KB Flash, 16Kb RAM, 84 I/O, NanoWatt 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ64GA106-I/MR

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (22K x 24)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Processor Series: PIC24FJ256GA110
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4.2
The PIC24F core has a separate, 16-bit wide data mem-
ory space, addressable as a single linear range. The
data space is accessed using two Address Generation
Units (AGUs), one each for read and write operations.
The data space memory map is shown in
All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the data space.
This gives a data space address range of 64 Kbytes or
32K words. The lower half of the data memory space
(that is, when EA<15> = 0) is used for implemented
memory addresses, while the upper half (EA<15> = 1) is
reserved for the program space visibility area (see
Section 4.3.3 “Reading Data From Program Memory
Using Program Space
FIGURE 4-3:
 2010 Microchip Technology Inc.
Note:
Data Address Space
Implemented
Data RAM
Data memory areas are not shown to scale.
DATA SPACE MEMORY MAP FOR PIC24FJ256GA110 FAMILY DEVICES
Visibility”).
Address
FFFFh
1FFFh
7FFFh
07FFh
47FFh
0001h
0801h
2001h
4801h
8001h
MSB
Figure
MSB
PIC24FJ256GA110 FAMILY
4-3.
Unimplemented
Program Space
Visibility Area
SFR Space
Read as ‘0’
Data RAM
LSB
PIC24FJ256GA110 family devices implement a total of
16 Kbytes of data memory. Should an EA point to a
location outside of this area, an all zero word or byte will
be returned.
4.2.1
The
byte-addressable, 16-bit wide blocks. Data is aligned
in data memory and registers as 16-bit words, but all
data space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even addresses, while
the Most Significant Bytes (MSBs) have odd
addresses.
data
DATA SPACE WIDTH
Address
0000h
07FEh
0800h
1FFEh
2000h
47FEh
4800h
7FFFh
8000h
FFFEh
LSB
memory
Space
SFR
space
Data Space
is
DS39905E-page 37
Near
organized
in