PIC24FJ64GA106-I/MR Microchip Technology, PIC24FJ64GA106-I/MR Datasheet - Page 185

• Manufacturer Part Number: PIC24FJ64GA106-I/MR
• Description: 16-bit, 16 MIPS, 64KB Flash, 16Kb RAM, 84 I/O, NanoWatt 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ64GA106-I/MR

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (22K x 24)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Processor Series: PIC24FJ256GA110
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

16.0
The Inter-Integrated Circuit (I
face useful for communicating with other peripheral or
microcontroller devices. These peripheral devices may
be serial EEPROMs, display drivers, A/D Converters,
etc.
The I
• Independent master and slave logic
• 7-bit and 10-bit device addresses
• General call address, as defined in the I
• Clock stretching to provide delays for the
• Both 100 kHz and 400 kHz bus specifications.
• Configurable address masking
• Multi-Master modes to prevent loss of messages
• Bus Repeater mode, allowing the acceptance of
• Automatic SCL
A block diagram of the module is shown in
16.1
The I
cannot be reassigned to alternate pins using Peripheral
Pin Select. To allow some flexibility with peripheral
multiplexing, the I2C2 module in 100-pin devices can
be reassigned to the alternate pins designated as
ASCL2 and ASDA2 during device configuration.
Pin assignment is controlled by the I2C2SEL Configu-
ration bit; programming this bit (= 0) multiplexes the
module to the ASCL2 and ASDA2 pins.
 2010 Microchip Technology Inc.
Note:
processor to respond to a slave data request
in arbitration
all messages as a slave regardless of the address
2
2
C module supports these features:
C modules are tied to fixed pin assignments and
INTER-INTEGRATED CIRCUIT
(I
Peripheral Remapping Options
2
Section 24. “Inter-Integrated Circuit
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F
(I
C™)
2
C™)” (DS39702).
Family
2
C) module is a serial inter-
Reference
2
C protocol
Figure
Manual”,
PIC24FJ256GA110 FAMILY
16-1.
16.2
The details of sending a message in Master mode
depends on the communications protocol for the device
being communicated with. Typically, the sequence of
events is as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Wait for and verify an Acknowledge from the
11. Enable master reception to receive serial
12. Generate an ACK or NACK condition at the end
13. Generate a Stop condition on SDAx and SCLx.
Assert a Start condition on SDAx and SCLx.
Send the I
with a write indication.
Wait for and verify an Acknowledge from the
slave.
Send the first data byte (sometimes known as
the command) to the slave.
Wait for and verify an Acknowledge from the
slave.
Send the serial memory address low byte to the
slave.
Repeat Steps 4 and 5 until all data bytes are
sent.
Assert a Repeated Start condition on SDAx and
SCLx.
Send the device address byte to the slave with
a read indication.
slave.
memory data.
of a received byte of data.
Communicating as a Master in a
Single Master Environment
2
C device address byte to the slave
DS39905E-page 185