SST89E58RD2-40-I-NJE Microchip Technology, SST89E58RD2-40-I-NJE Datasheet - Page 53

• Manufacturer Part Number: SST89E58RD2-40-I-NJE
• Description: 4.5 To 5.5V FlashFlex 8-bit 8051 Microcontroller 44 PLCC TUBE
• Manufacturer: Microchip Technology
• Series: FlashFlex®r

Specifications of SST89E58RD2-40-I-NJE

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LCC (J-Lead)
• Processor Series: FlashFlex51
• Core: C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

FlashFlex MCU
SST89E54RD2A/RDA / SST89E58RD2A/RDA
8.3.2 16-Bit Software Timer Mode
The 16-bit software timer mode is used to trigger interrupt
routines, which must occur at periodic intervals. It is setup
by setting both the ECOM and MAT bits in the module’s
CCAPMn register. The PCA timer will be compared to the
module’s capture registers (CCAPnL and CCAPnH) and
when a match occurs, an interrupt will occur, if the CCFn
(CCON SFR) and the ECCFn (CCAPMn SFR) bits for the
module are both set.
©2008 Silicon Storage Technology, Inc.
Write to
CCAPnH
FIGURE
1
CCAPnL
Write to
8-3: PCA Compare Mode (Software Timer)
0
Reset
Enable
CCAPnH
PCA Timer/Counter
16-bit Comparator
CH
CF
CCAPnL
ECOMn CAPPn CAPNn MATn
CR
CL
0
53
Match
If necessary, a new 16-bit compare value can be loaded
into CCAPnH and CCAPnL during the interrupt routine.
The user should be aware that the hardware temporarily
disables the comparator function while these registers are
being updated so that an invalid match will not occur. Thus,
it is recommended that the user write to the low byte first
(CCAPnL) to disable the comparator, then write to the high
byte (CCAPnH) to re-enable it. If any updates to the regis-
ters are done, the user may want to hold off any interrupts
from occurring by clearing the EA bit. (See Figure 8-3)
CCF4
0
CCF3
TOGn
CCF2
0
PWMn ECCFn
CCF1
0
CCF0
CCON
S71339-02-000
CCAPMn
n=0 to 4
PCA Interrupt
Data Sheet
1339 F25.0
02/08