SC16C852VIET-G NXP Semiconductors, SC16C852VIET-G Datasheet
SC16C852VIET-G
Specifications of SC16C852VIET-G
Related parts for SC16C852VIET-G
SC16C852VIET-G Summary of contents
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SC16C852V 1.8 V dual UART, 5 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA), and XScale VLIO bus interface Rev. 04 — 14 January 2008 1. General description The SC16C852V is a 1.8 V, low power dual channel Universal Asynchronous Receiver ...
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... Ordering information Table 1. Type number SC16C852VIBS HVQFN48 plastic thermal enhanced very thin quad flat package; SC16C852VIET TFBGA36 plastic thin fine-pitch ball grid array package; 36 balls; SC16C852V_4 Product data sheet Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface Ordering information ...
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... NXP Semiconductors 4. Block diagram SC16C852VIBS AD0 to AD7 DATA BUS IOR IOW CONTROL RESET LLA REGISTER CS SELECT LOWPWR CONTROL INTA, INTB INTERRUPT TXRDYA, TXRDYB CONTROL RXRDYA, RXRDYB Fig 1. Block diagram of SC16C852V (HVQFN48 package) SC16C852V_4 Product data sheet Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface ...
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... NXP Semiconductors SC16C852VIET AD0 to AD7 DATA BUS IOR AND IOW CONTROL RESET LOGIC LLA REGISTER CS SELECT LOGIC POWER DOWN LOWPWR CONTROL INTERRUPT INTA, INTB CONTROL LOGIC Fig 2. Block diagram of SC16C852V (TFBGA36 package) SC16C852V_4 Product data sheet Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface ...
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... Pin configuration for HVQFN48 ball A1 index area Pin configuration for TFBGA36 Rev. 04 — 14 January 2008 SC16C852V 36 RESET 35 DTRB 34 DTRA 33 RTSA 32 OP2A 31 RXRDYA 30 INTA 29 INTB 28 LLA 27 n.c. 26 n.c. 25 n.c. 002aac351 SC16C852VIET 002aac350 Transparent top view © NXP B.V. 2008. All rights reserved ...
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... NXP Semiconductors Fig 5. 5.2 Pin description Table 2. Pin description Symbol Pin TFBGA36 HVQFN48 AD0 A3 44 AD1 B3 45 AD2 A2 46 AD3 B2 47 AD4 A1 48 AD5 B1 1 AD6 C3 2 AD7 C1 3 CDA B4 40 CDB CTSA A6 38 CTSB F6 23 DSRA A5 39 DSRB E4 20 DTRA ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin TFBGA36 HVQFN48 INTA D5 30 INTB D6 29 IOR F4 19 IOW E3 15 LLA E6 28 LOWPWR F1 12 n.c. - 11, 24, 25, 26, 27, 37 OP2A - 32 OP2B - 9 RESET B5 36 RIA A4 41 RIB F5 21 SC16C852V_4 Product data sheet Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin TFBGA36 HVQFN48 RTSA C6 33 RTSB E5 22 RXA D1 5 RXB C2 4 RXRDYA - 31 RXRDYB - 18 TXA D2 7 TXB E1 8 TXRDYA - 43 TXRDYB - [ XTAL1 D3 13 XTAL2 F2 14 [1] HVQFN48 package die supply ground is connected to both V ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region ...
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... NXP Semiconductors 6. Functional description The SC16C852V provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to form a data character (character orientated protocol) ...
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... NXP Semiconductors 6.2 Extended mode (128-byte FIFO) The device is in the extended mode when any of these four registers contains any value other than 0: FLWCNTH, FLWCNTL, TXINTLVL, RXINTLVL. 6.3 Internal registers The SC16C852V provides two sets of internal registers (A and B) consisting of 25 registers each for monitoring and controlling the functions of each channel of the UART ...
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... NXP Semiconductors [2] These registers are accessible only when LCR[ logic 1. [3] Second special registers are accessible only when EFCR[ [4] Enhanced feature registers are only accessible when LCR = 0xBF. [5] First extra feature registers are only accessible when EFCR[2:1] = 01b. [6] Second extra feature registers are only accessible when EFCR[2:1] = 10b. ...
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... NXP Semiconductors When AFCR1[2] is set to 1, then the function of CTSx pin is mapped to the DSRx pin, and the function of RTS is mapped to DTRx pin. DSRx and DTRx pins will behave as described above for CTSx and RTSx. With the automatic hardware flow control function enabled, an interrupt is generated when the receive FIFO reaches the programmed trigger level ...
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... NXP Semiconductors In the event that the receive buffer is overfilling, the SC16C852V automatically sends an Xoff character (when enabled) via the serial TX output to the remote UART. The SC16C852V sends the Xoff1/Xoff2 characters as soon as the number of received data in the receive FIFO passes the programmed trigger level. To clear this condition, the SC16C852V will transmit the programmed Xon1/Xon2 characters as soon as the number of characters in the receive FIFO drops below the programmed trigger level ...
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... NXP Semiconductors 6.9 Programmable baud rate generator The SC16C852V UART contains a programmable rational baud rate generator that takes any clock input and divides divisor in the range between 1 and (2 SC16C852V offers the capability of dividing the input frequency by rational divisor. The fractional part of the divisor is controlled by the CLKPRES register in the First Extra Register Set ...
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... NXP Semiconductors Fig 7. Fig 8. Table 6. Output baud rate (bit/ 110 150 300 600 1200 2400 3600 4800 7200 9600 19.2 k 38.4 k 57.6 k 115.2 k SC16C852V_4 Product data sheet Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface XTAL1 XTAL2 X1 1.8432 MHz ...
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... NXP Semiconductors 6.10 DMA operation The SC16C852V FIFO trigger level provides additional flexibility to the user for block mode operation. The user can optionally operate the transmit and receive FIFOs in the DMA mode (FCR[3]). The DMA mode affects the state of the RXRDYx and TXRDYx output pins ...
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... NXP Semiconductors SC16C852V AD0 to AD7 DATA BUS IOR AND IOW CONTROL RESET LOGIC LLA REGISTER CS SELECT LOGIC POWER DOWN LOWPWR CONTROL INTA, INTB INTERRUPT TXRDYA, TXRDYB CONTROL RXRDYA, RXRDYB LOGIC Fig 9. Internal Loopback mode diagram SC16C852V_4 Product data sheet Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface ...
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... NXP Semiconductors 6.12 Sleep mode Sleep mode is an enhanced feature of the SC16C852V UART enabled when EFR[4], the enhanced functions bit, is set and when IER[4] of both channels are set. 6.12.1 Conditions to enter Sleep mode Sleep mode is entered when: • Modem input pins are not toggling. ...
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... NXP Semiconductors 6.14 RS-485 features 6.14.1 Auto RS-485 RTS control Normally the RTSx pin is controlled by MCR bit hardware flow control is enabled, the logic state of the RTSx pin is controlled by the hardware flow control circuitry. EFCR2 register bit 4 will take the precedence over the other two modes; once this bit is set, the transmitter will control the state of the RTSx pin ...
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... NXP Semiconductors 6.14.3.2 Auto address detection If Special Character Detect is enabled (EFR[5] is set and the XOFF2 register contains the address byte), the receiver will try to detect an address byte that matches the programmed character in the XOFF2 register. If the received byte is a data byte or an address byte that does not match the programmed character in the XOFF2 register, the receiver will discard these data ...
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Table 9. SC16C852V internal registers [ Register Default Bit 7 [2] General register set RHR XX bit THR XX bit IER 00 CTS interrupt 0 1 ...
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Table 9. SC16C852V internal registers …continued [ Register Default Bit 7 [6] Enhanced register set EFR 00 Auto CTS Xon-1 00 bit Xon-2 00 bit 15 1 ...
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... NXP Semiconductors 7.1 Transmit (THR) and Receive (RHR) Holding Registers The serial transmitter section consists of an 8-bit Transmit Holding Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data bus (AD7 to AD0) to the transmit FIFO. The THR empty fl ...
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... NXP Semiconductors Table 10. Bit Symbol Description 1 IER[1] 0 IER[0] 7.2.1 IER versus transmit/receive FIFO interrupt mode operation When the receive FIFO is enabled (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are enabled, the receive interrupts and register status will reflect the following: • ...
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... NXP Semiconductors 7.3 FIFO Control Register (FCR) This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger levels, and select the DMA mode. 7.3.1 DMA mode 7.3.1.1 Mode 0 (FCR bit this mode, Transmit Ready (TXRDY) will logic 0 whenever the FIFO (THR, if FIFO is not enabled) is empty ...
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... NXP Semiconductors Table 11. Bit 3 (cont [1] For 128-byte FIFO mode, refer to [2] For 128-byte FIFO mode, refer to Table 12. FCR[ [1] When RXINTLVL or TXINTLVL or FLWCNTH or FLWCNTL contains any value other than 0x00, receive and transmit trigger levels are set by RXINTLVL, TXINTLVL; see Table 13. ...
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... NXP Semiconductors 7.4 Interrupt Status Register (ISR) The SC16C852V provides six levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced ...
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... NXP Semiconductors 7.5 Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. Table 16. Bit 7 6 5:3 2 1:0 Table 17 ...
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... NXP Semiconductors 7.6 Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. Table 20. Bit Symbol Description 7 MCR[7] Clock select 6 MCR[6] IR enable (see 5 MCR[5] Reserved; set to ‘0’. 4 MCR[4] Loopback. Enable the local Loopback mode (diagnostics). In this mode the ...
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... NXP Semiconductors 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C852V and the CPU. Table 22. Bit Symbol 7 LSR[7] 6 LSR[6] 5 LSR[5] 4 LSR[4] 3 LSR[3] 2 LSR[2] 1 LSR[1] 0 LSR[0] SC16C852V_4 Product data sheet Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface ...
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... NXP Semiconductors 7.8 Modem Status Register (MSR) This register shares the same address as EFCR register. This is a read-only register and it provides the current state of the control interface signals from the modem, or other peripheral device to which the SC16C852V is connected. Four bits of this register are used to indicate the changed information ...
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... NXP Semiconductors 7.9 Extra Feature Control Register (EFCR) This is a write-only register, and it allows the software access to these registers: First Extra Register Set, Second Extra Register Set, Transmit FIFO Level Counter (TXLVLCNT), and Receive FIFO Level Counter (RXLVLCNT). Table 24. Bit 7:3 ...
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... NXP Semiconductors 7.14 Enhanced Feature Register (EFR) Enhanced features are enabled or disabled using this register. Bit 0 through bit 4 provide single or dual character software flow control selection. When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words are concatenated into two sequential numbers ...
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... NXP Semiconductors Table 26. Cont [1] When using a software flow control the Xon/Xoff characters cannot be used for data transfer. 7.15 Transmit Interrupt Level register (TXINTLVL) This 8-bit register is used store the transmit FIFO trigger levels used for DMA and interrupt generation. Trigger levels from 1 to 128 can be programmed with a granularity of 1. ...
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... NXP Semiconductors 7.17 Flow Control Trigger Level High (FLWCNTH) This 8-bit register is used to store the receive FIFO high threshold levels to start/stop transmission during hardware/software flow control. register bit settings; see Table 29. Bit 7:0 [1] For 32-byte FIFO mode, refer to 7.18 Flow Control Trigger Level Low (FLWCNTL) This 8-bit register is used to store the receive FIFO low threshold levels to start/stop transmission during hardware/software fl ...
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... NXP Semiconductors 7.20 RS-485 turn-around time delay (RS485TIME) The value in this register controls the turn-around time of the external line transceiver in bit time. In automatic 9-bit mode, the RTSA/RTSB or DTRA/DTRB pin is used to control the direction of the line driver, after the last bit of data has been shifted out of the transmit shift register the UART will count down the value in this register ...
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... NXP Semiconductors 7.22 Advanced Feature Control Register 2 (AFCR2) Table 34. Bit 7 SC16C852V_4 Product data sheet Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface Advanced Feature Control Register 2 bits description Symbol Description AFCR2[7:6] reserved AFCR2[5] RTSInvert. Invert RTS or DTR signal in auto 9-bit mode. ...
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... NXP Semiconductors 7.23 SC16C852V external reset condition and software reset These two reset methods are identical and will reset the internal registers as indicated in Table 35. Table 35. Register IER FCR ISR LCR MCR LSR MSR EFCR SPR DLL DLM TXLVLCNT RXLVLCNT EFR Xon-1 ...
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... NXP Semiconductors 8. Limiting values Table 37. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol amb T stg P /pack total power dissipation per tot [1] V should not exceed 2 Static characteristics Table 38 + amb Symbol V IL(clk) V IH(clk LIL I LIH I L(clk DD(sleep) I DD(lp [1] Except XTAL2, V [2] Sleep current might be higher if there is any activity on the UART data bus during Sleep mode ...
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... NXP Semiconductors 10. Dynamic characteristics Table 39. Dynamic characteristics + 1. 1.95 V; unless otherwise specified. amb DD Symbol Parameter f frequency on pin XTAL1 XTAL1 t delay time from CS to LLA HIGH d(CS-LLAH) t set-up time from address to LLA HIGH su(A-LLAH) t LLA pulse width time w(LLA) t address hold time after LLA HIGH ...
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... NXP Semiconductors 10.1 Timing diagrams AD7 to AD0 CS LLA IOW Fig 10. General write timing AD7 to AD0 CS LLA IOR Fig 11. General read timing SC16C852V_4 Product data sheet Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface upper address lower address t su(A-LLAH) ...
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... NXP Semiconductors IOW RTSA, RTSB change of state DTRA, DTRB CDA, CDB CTSA, CTSB DSRA, DSRB INTA, INTB IOR RIA, RIB Fig 12. Modem input/output timing external clock -------------- - XTAL1 t w clk Fig 13. External clock timing SC16C852V_4 Product data sheet Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface ...
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... NXP Semiconductors RXA, RXB INTA, INTB IOR Fig 14. Receive timing RXA, RXB RXRDYA RXRDYB IOR Fig 15. Receive ready timing in non-FIFO mode SC16C852V_4 Product data sheet Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface start bit data bits ( data bits ...
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... NXP Semiconductors RXA, RXB RXRDYA RXRDYB IOR Fig 16. Receive ready timing in FIFO mode TXA, TXB INTA, INTB active IOW Fig 17. Transmit timing SC16C852V_4 Product data sheet Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface start bit data bits ( ...
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... NXP Semiconductors TXA, TXB IOW active AD0 to AD7 byte #1 t d(IOW-TXRDYH) TXRDYA TXRDYB Fig 18. Transmit ready timing in non-FIFO mode TXA, TXB IOW active byte #32 or AD0 to AD7 byte #128 TXRDYA TXRDYB Fig 19. Transmit ready timing in FIFO mode (DMA mode ‘1’) ...
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... NXP Semiconductors TX data IrDA TX data Fig 20. Infrared transmit timing IrDA RX data RX data Fig 21. Infrared receive timing SC16C852V_4 Product data sheet Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface UART frame start bit time bit time start Rev. 04 — 14 January 2008 ...
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... NXP Semiconductors 11. Package outline HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 0.85 mm terminal 1 index area terminal 1 48 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max 0.05 0. 0.2 0.00 0.15 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included ...
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... NXP Semiconductors TFBGA36: plastic thin fine-pitch ball grid array package; 36 balls; body 3.5 x 3.5 x 0.8 mm ball A1 index area 1 ball A1 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.25 0.90 0.35 mm 1.15 0.15 0.75 0.25 OUTLINE VERSION IEC - - - SOT912-1 Fig 23. Package outline SOT912-1 (TFBGA36) ...
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... NXP Semiconductors 12. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 12.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 12.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 24. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 13. Abbreviations Table 42. Acronym CPU DLL DLM DMA FIFO IrDA ISDN LSB MSB PCB RoHS ...
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... NXP Semiconductors 14. Revision history Table 43. Revision history Document ID Release date SC16C852V_4 20080114 • Modifications: Table 9 “SC16C852V internal – R/W value for register TXLVLCNT changed from “R/W” to “R” – R/W value for register RXLVLCNT changed from “R/W” to “R” ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 Functional description . . . . . . . . . . . . . . . . . . . 9 6.1 UART A-B functions . . . . . . . . . . . . . . . . . . . . . 9 6.2 Extended mode (128-byte FIFO 6.3 Internal registers 6.4 FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 11 6.4.1 32-byte FIFO mode ...