SC16C852VIET-G NXP Semiconductors, SC16C852VIET-G Datasheet - Page 7

• Manufacturer Part Number: SC16C852VIET-G
• Manufacturer: NXP Semiconductors

Specifications of SC16C852VIET-G

• Transmitter And Receiver Fifo Counter: Yes
• Data Rate: 5Mbps
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Number Of Channels: 2
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 2.
SC16C852V_4
Product data sheet
Symbol
INTA
INTB
IOR
IOW
LLA
LOWPWR F1
n.c.
OP2A
OP2B
RESET
RIA
RIB
Pin description
Pin
TFBGA36
D5
D6
F4
E3
E6
-
-
-
B5
A4
F5
HVQFN48
30
29
19
15
28
12
11, 24,
25, 26,
27, 37
32
9
36
41
21
…continued
Type Description
O
O
I
I
I
I
-
O
O
I
I
I
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
Channel A interrupt output. The output state is defined by the user through
the software setting of MCR[3]. INTA is set to the active mode when MCR[3] is
set to a logic 1. INTA is set to the 3-state mode when MCR[3] is set to a logic 0.
See
Channel B interrupt output. The output state is defined by the user through
the software setting of MCR[3]. INTB is set to the active mode when MCR[3] is
set to a logic 1. INTB is set to the 3-state mode when MCR[3] is set to a logic 0.
See
Read strobe (active LOW). A HIGH to LOW transition on this signal starts the
read cycle. The SC16C852V reads a byte from the internal register and puts
the byte on the data bus for the host to retrieve.
Write strobe (active LOW). A HIGH to LOW transition on this signal starts the
write cycle, and a LOW to HIGH transition transfers the data on the data bus to
the internal register.
Latch Lower Address (active LOW). A logic LOW on this pin puts the VLIO
interface in the address phase of the transaction, where the lower 8 bits of the
VLIO (specifying the UART register and the channel address) are loaded into
the address latch of the device through the AD7 to AD0 bus. A logic HIGH puts
the VLIO interface in the data phase where data can are transferred between
the host and the UART.
Low Power. When asserted (active HIGH), the device immediately goes into
low power mode. The oscillator is shut-off and some host interface pins are
isolated from the host’s bus to reduce power consumption. The device only
returns to normal mode when the LOWPWR pin is de-asserted. On the
negative edge of a de-asserting LOWPWR signal, the device is automatically
reset and all registers return to their default reset states. This pin has an
internal pull-down resistor, therefore, it can be left unconnected.
not connected
Output 2 (user-defined). This function is associated with individual channels,
A through B. The state at these pin(s) are defined by the user and through
MCR register bit 3. INTA, INTB are set to the active mode and OP2A/OP2B to
logic 0 when MCR[3] is set to a logic 1. INTA, INTB are set to the 3-state mode
and OP2A/OP2B to a logic 1 when MCR[3] is set to a logic 0 (see
“Modem Control Register bits
the INTA, INTB operation and OP2A/OP2B outputs, only one function should
be used at one time, interrupt or OP function.
Master reset (active LOW). A reset pulse will reset the internal registers and
all the outputs. The SC16C852V transmitter outputs and receiver inputs will be
disabled during reset time. (See
condition and software reset”
Ring Indicator (active LOW). These inputs are associated with individual
UART channels, A through B. A logic 0 on this pin indicates the modem has
received a ringing signal from the telephone line. A logic 1 transition on this
input pin will generate an interrupt.
Table
Table
Rev. 04 — 14 January 2008
21.
21.
for initialization details.)
description”, bit 3). Since these bits control both
Section 7.23 “SC16C852V external reset
SC16C852V
© NXP B.V. 2008. All rights reserved.
Table 20
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