SC16C852VIET-G NXP Semiconductors, SC16C852VIET-G Datasheet - Page 8

• Manufacturer Part Number: SC16C852VIET-G
• Manufacturer: NXP Semiconductors

Specifications of SC16C852VIET-G

• Transmitter And Receiver Fifo Counter: Yes
• Data Rate: 5Mbps
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Number Of Channels: 2
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 2.
[1]
SC16C852V_4
Product data sheet
Symbol
RTSA
RTSB
RXA
RXB
RXRDYA
RXRDYB
TXA
TXB
TXRDYA
TXRDYB
V
V
XTAL1
XTAL2
DD
SS
HVQFN48 package die supply ground is connected to both V
ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be
soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the PCB in the thermal pad region.
Pin description
Pin
TFBGA36
C6
E5
D1
C2
-
-
D2
E1
-
-
C4
D4
D3
F2
HVQFN48
33
22
5
4
31
18
7
8
43
6
42
17
13
14
[1]
…continued
Type Description
O
O
I
I
O
O
O
O
O
O
I
I
I
O
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
Request to Send (active LOW). These outputs are associated with individual
UART channels, A through B. A logic 0 on the RTS pin indicates the transmitter
has data ready and waiting to send. Writing a logic 1 in the modem control
register MCR[1] will set this pin to a logic 0, indicating data is available. After a
reset this pin will be set to a logic 1.
Receive data A, B. These inputs are associated with individual serial channel
data to the SC16C852V receive input circuits, A through B. The RX signal will
be a logic 1 during reset, idle (no data), or when not receiving data. During the
local Loopback mode, the RX input pin is disabled and TX data is connected to
the UART RX input, internally.
Receive Ready A, B (active LOW). This function provides the RX FIFO/RHR
status for individual receive channels (A to B). RXRDYn is primarily intended
for monitoring DMA mode 1 transfers for the receive data FIFOs. A logic 0
indicates there is a receive data to read/upload, that is, receive ready status
with one or more RX characters available in the FIFO/RHR. This pin is a logic 1
when the FIFO/RHR is empty or when the programmed trigger level has not
been reached. This signal can also be used for single mode transfers (DMA
mode 0).
Transmit data A, B. These outputs are associated with individual serial
transmit channel data from the SC16C852V. The TX signal will be a logic 1
during reset, idle (no data), or when the transmitter is disabled. During the local
Loopback mode, the TX output pin is disabled and TX data is internally
connected to the UART RX input.
Transmit Ready A, B (active LOW). These outputs provide the TX FIFO/THR
status for individual transmit channels (A to B). TXRDYn is primarily intended
for monitoring DMA mode 1 transfers for the transmit data FIFOs. An individual
channel’s TXRDYA, TXRDYB buffer ready status is indicated by logic 0, that is,
at lease one location is empty and available in the FIFO or THR. This pin goes
to a logic 1 (DMA mode 1) when there are no more empty locations in the FIFO
or THR. This signal can also be used for single mode transfers (DMA mode 0).
Power supply input.
Signal and power ground.
Crystal or external clock input. Functions as a crystal input or as an external
clock input. A crystal can be connected between this pin and XTAL2 to form an
internal oscillator circuit. Alternatively, an external clock can be connected to
this pin to provide custom data rates (see
rate
Output of the crystal oscillator or buffered clock. (See also XTAL1.) Crystal
oscillator output or buffered clock output. Should be left open if an external
clock is connected to XTAL1.
generator”). See
Rev. 04 — 14 January 2008
SS
pin and exposed center pad. V
Figure
7.
Section 6.9 “Programmable baud
SS
pin must be connected to supply
SC16C852V
© NXP B.V. 2008. All rights reserved.
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